Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2011-07-26
2011-07-26
Pham, Thanh V (Department: 2894)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S149000, C438S151000, C438S171000, C438S459000, C257S638000
Reexamination Certificate
active
07985633
ABSTRACT:
Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.
REFERENCES:
patent: 5212397 (1993-05-01), See et al.
patent: 5858831 (1999-01-01), Sung
patent: 6063652 (2000-05-01), Kim
patent: 6133130 (2000-10-01), Lin et al.
patent: 6214676 (2001-04-01), Jun et al.
patent: 6472265 (2002-10-01), Hsieh
patent: 6509218 (2003-01-01), Yeh et al.
patent: 6537891 (2003-03-01), Dennison et al.
patent: 6818496 (2004-11-01), Dennison et al.
patent: 7195972 (2007-03-01), Chidambarrao et al.
patent: 2002/0182801 (2002-12-01), Shimazaki et al.
R. W. Keyes, “Effect of Randomness in the Distribution of Impurity Ions on FET Thresholds in Integrated Electronics,” IEEE Journal of Solid-State Circuits, vol. SC-10, pp. 245-247, Aug. 1975.
R. Katsumata et al., “Fin-Array-FET on bulk silicon for sub-100 nm Trench Capacitor DRAM,” Symposium on VLSI Technology, 2003.
M. Yoshida et al., “A Full FinFET DRAM Core Integration Technology Using a Simple Selective Fin Formation Technique,” Symposium on VLSI Technology, 2006.
H. Kawasaki et al., “Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm node and beyond,” Symposium on VLSI Technology, 2006.
G. Wang et al., A 0.127 μm2 High Performance 65nm SOI Based embedded DRAM for on-Processor Applications, International Electron Devices Meeting, 2006.
Cai Jin
Chang Josephine
Chang Leland
Ji Brian L.
Koester Steven John
Alexanian Vazken
Chang, LLC Michael J.
International Business Machines - Corporation
Ligai Maria
Pham Thanh V
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