Search
Selected: D

Double silicon-on-insulator (SOI) metal oxide semiconductor...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Double silicon-on-insulator (SOI) metal oxide semiconductor...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Double SOI device with recess etch and epitaxy

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Double spacer salicide MOS process and device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Double-bit non-volatile memory structure and corresponding...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Double-doped polysilicon floating gate

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Double-doped polysilicon floating gate

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Double-doped polysilicon floating gate

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Double-gate FET with planarized surfaces and self-aligned...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Double-gate FETs (Field Effect Transistors)

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Double-gate transistor formed in a thermal process

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Double-gate transistor with enhanced carrier mobility

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Double-gate vertical MOSFET transistor and fabrication method

Semiconductor device manufacturing: process – Making field effect device having pair of active regions...
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Double-side corrugated cylindrical capacitor structure of high d

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Double-sided capacitor structure for a semiconductor device...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Drain and source engineering for ESD-protection transistors

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Drain extended MOS devices with self-aligned floating region...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Drain extended MOS transistors with multiple capacitors and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Drain extension regions in low voltage lateral DMOS devices

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Drain leakage reduction by indium transient enchanced...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0
  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.