Double-doped polysilicon floating gate

Details Double-doped polysilicon floating gate Double-doped polysilicon floating gate

2002-08-29

2004-05-18

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S532000, C438S592000

Reexamination Certificate

active

06737320

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a semiconductor memory element, and, more particularly, to forming a double-doped polysilicon floating gate in a semiconductor memory element.
2. Description of the Related Art
Data storage devices in modern integrated circuits generally include a plurality of memory cells formed above a semiconductor substrate, such as silicon. For example, a semiconductor memory array may include 256K (256×1024) memory cells. Electrically conducting lines are also formed in the semiconductor substrate and coupled to the memory cells. Bits of data are stored in the memory cells, for example, by providing a voltage or a current to a plurality of bit lines and a plurality of orthogonal word lines that are electrically coupled to the memory cells. In one embodiment, the memory cells are formed from non-volatile components, such as a floating gate transistor. For example, floating gates are used to form flash memory cells, EEPROM memory cells, and the like.
A traditional flash memory cell
100
is shown in FIG.
1
. The flash memory cell
100
includes a source
110
and a drain
115
formed in a substrate
120
, which may be comprised of a variety of semiconductor materials. For example, the substrate
120
may be comprised of silicon, which may be doped with n-type or p-type dopants. During operation of the flash memory cell
100
, a channel
125
will be established in the substrate
120
between the source and drain regions
110
,
115
. The flash memory cell
100
also includes a first insulating layer
130
that is often called a tunnel oxide layer, a floating gate
105
, a second insulating layer
135
that is often called an inter-poly insulation layer, and a control gate
140
. The insulating layers
130
,
135
may be dielectric layers. In the interest of clarity, the techniques for forming the various gates and layers described above, which are well known to those of ordinary skill in the art and are not material to the present invention, will not be discussed herein.
To program the flash memory cell
100
, a first voltage V
1
is provided to the control gate
140
. A second voltage V
2
, which is usually smaller than the first voltage V
1
, is provided to the drain
115
, and third and fourth voltages V
3
, V
4
, which are generally smaller than the second voltage V
2
, are provided to the source
110
and the substrate
120
, respectively. For example, a first voltage V
1
of about 8-10 volts is provided to the control gate
140
, a second voltage V
2
of about 4-5 volts is provided to the drain
115
, and the source
110
and substrate
120
are grounded.
The voltage of about 8 volts on the control gate
140
and the resulting voltage differential of about 4 volts between the source
110
and the drain
115
will cause a current of electrons to flow through the channel
125
from the source
110
to the drain
115
. As electrons flow through the channel
125
, the voltage differential of about 8 volts between the control gate
140
and the substrate
120
will cause a portion of the electrons to “tunnel” through the first insulating layer
130
to the floating gate
105
and become trapped or stored therein. The presence or absence of the collected electrons in the floating gate
105
may be detected in a reading operation well known to those of ordinary skill in the art. For example, the presence of collected electrons in the floating gate
105
may be determined to represent a logic-low state, whereas the absence of collected electrons in the floating gate
105
may be determined to represent a logic-high state, or vice versa.
To erase the flash memory cell
100
once it has been programmed, different voltage levels are generally applied to the flash memory cell
100
. For example, a first voltage V
1
of about negative 9 volts is provided to the control gate
140
, a third voltage V
3
of about +9 volts. is provided to the source
110
, and a fourth voltage V
4
of about +9 volts is provided to the substrate
120
. The resulting voltage differential of about 18 volts between the control gate
140
and the substrate
120
causes a portion of the electrons in the floating gate
105
to “tunnel” through the first insulating layer
130
to the substrate
120
, thus discharging the floating gate
105
. In one embodiment, a second voltage V
2
may be allowed to float.
Although the flash memory cell
100
described above generally traps or stores electrons for a relatively long time compared to volatile memory cells such as DRAMs, and the like, a leakage current formed of electrons tunneling from the floating gate
105
to the substrate
120
may eventually discharge the flash memory cell
100
. Furthermore, the effects of a leakage current generally increase as the size of non-volatile memory cells, such as the flash memory cell
100
, decrease. Thus, future advances in semiconductor processing technology that tend to reduce the size of non-volatile memory cells will only exacerbate this problem.
The effects of the leakage current may be reduced by improving the insulating capabilities of the first and/or second insulating layers
130
,
135
surrounding the floating gate
105
. For example, the first and/or second insulating layers
130
,
135
may be made thicker. However, such an approach adversely impacts the programming and erasing operations of the flash memory cell
100
.
A method and structure are needed to reduce the effects of leakage current without unduly affecting the programming, reading, and/or erasure of the flash memory cell
100
.
SUMMARY OF THE INVENTION
In one aspect of the instant invention, a method is provided for forming a double-doped polysilicon floating gate in a semiconductor memory element. The method includes forming a first dielectric layer on a semiconductor substrate and forming a floating gate above the first dielectric layer, the floating gate comprised of a first layer doped with a first type of dopant material and a second layer doped with a second type of dopant material that is opposite the first type of dopant material in the first layer. The method further includes forming a second dielectric layer above the floating gate, forming a control gate above the second dielectric layer, and forming a source and a drain in the substrate.
In one aspect of the present invention, an apparatus is provided. The apparatus includes a first dielectric layer formed on a semiconductor substrate and a double-doped floating gate formed above the dielectric layer. The apparatus further includes a second dielectric layer formed above the double-doped floating gate, a control gate formed above the second dielectric layer, and a source and a drain formed in the substrate.


REFERENCES:
patent: 3731163 (1973-05-01), Shuskus
patent: 4682407 (1987-07-01), Wilson et al.
patent: 4914046 (1990-04-01), Tobin et al.
patent: 5691560 (1997-11-01), Sakakibara
patent: 5841161 (1998-11-01), Lim et al.
patent: 6111287 (2000-08-01), Arai
Muller, et al., Device Electronics for Integrated Circuits, 2nd edition, 1986, John Wiley & Sons, New York, pp. 80.*
Horiguchi, Usuki, Goto, Futatsugi, Sugii and Yokoyama: “Retention Time Enhancement in Direct Tunneling Memory (DTM) Utilizing Floating Gate Depletion by Diffusion Stopper,” pp. 458-458.3.

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