Double spacer salicide MOS process and device

Details Double spacer salicide MOS process and device Double spacer salicide MOS process and device

1996-09-24

1998-10-20

Graybill, David

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, 438592, 438655, H01L 21336, H01L 213205

Patent

active

058245880

ABSTRACT:
A double spacer salicide MOS device structure and a process for preparing such a device. The double spacer salicide device has a LDD structure. The first sidewall spacer disposed adjacent to the gate structure of the MOS device is higher than the gate. During the salicide process, the first sidewall spacer is used to effectively isolate the gate from the source/drain. The second sidewall spacer disposed adjacent to the first sidewall spacer is used to form the LDD structure.

REFERENCES:
patent: 5330925 (1994-07-01), Lee et al.
patent: 5352631 (1994-10-01), Sitaram et al.
patent: 5424234 (1995-06-01), Kwon
patent: 5468665 (1995-11-01), Lee et al.
patent: 5496751 (1996-03-01), Wei et al.
patent: 5518945 (1996-05-01), Bracchitta et al.
Wolf, Stanley "Silicon Processing For The VLSI Era Vol. 1: Process Technology", Lattice Press, pp. 191-194 no month 1986.

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