Double-doped polysilicon floating gate

Details Double-doped polysilicon floating gate Double-doped polysilicon floating gate

2008-03-04

2008-03-04

Luu, Chuong A. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S592000, C438S258000

Reexamination Certificate

active

10649050

ABSTRACT:
The present invention provides a method and apparatus for forming a double-doped polysilicon floating gate in a semiconductor memory element. The method includes forming a first dielectric layer on a semiconductor substrate and forming a floating gate above the first dielectric layer, the floating gate comprised of a first layer doped with a first type of dopant material and a second layer doped with a second type of dopant material that is opposite the first type of dopant material in the first layer. The method further includes forming a second dielectric layer above the floating gate, forming a control gate above the second dielectric layer, and forming a source and a drain in the substrate.

REFERENCES:
patent: 5841161 (1998-11-01), Lim et al.
patent: 6111287 (2000-08-01), Arai
patent: 6737320 (2004-05-01), Chen et al.
Horiguchi, Usuki, Goto, Futatsugi, Sugii and Yokoyama: “Retention Time Enhancement in Direct Tunneling Memory (DTM) Utilizing Floating Gate Depletion by Diffusion Stopper,” pp. 458-458.3, date is unknown.

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