Double silicon-on-insulator (SOI) metal oxide semiconductor...

Details Double silicon-on-insulator (SOI) metal oxide semiconductor... Double silicon-on-insulator (SOI) metal oxide semiconductor...

2008-07-01

2008-07-01

Lebentritt, Michael S. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C257SE21561, C257SE21703

Reexamination Certificate

active

07393732

ABSTRACT:
A SOI MOSFET structure having a reduced step height between the various semiconductor layers without adversely affecting the junction capacitance of the semiconductor device formed on the uppermost semiconductor layer as well as a method of fabricating the same are provided. The structure of the present invention includes an elevated device region having at least one semiconductor device located on a second semiconductor layer. The elevated device region further includes a source/drain junction that extends from the second semiconductor layer down to a first buried insulator layer that is located on an upper surface of the semiconductor substrate. The structure also includes a recessed device region having at least one semiconductor device located atop a first semiconductor layer which is located on an upper surface of the first buried insulator. An isolation region separates the elevated device region from the recessed device region.

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