Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
1999-10-14
2001-09-04
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S286000, C438S527000
Reexamination Certificate
active
06284579
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of microelectronics fabrications. More particularly, the invention relates to the field of microelectronics fabrications employing low power field effect transistor (FET) devices.
2. Description of the Related Art
Microelectronics fabrications may combine various kinds of electronic devices and components within their design. One of the most important kinds of electronic device encountered in modern microelectronics is the field effect transistor (FET), which employs a gate electrode insulated from a conductive channel formed between source and drain electrode regions. In one type of FET commonly employed in modern microelectronics fabrications, the source and drain electrode regions may be fabricated by forming n-type regions in a p-type silicon substrate to form n-type metal oxide silicon field effect transistor (NMOSFET). When fabricated with light n-type doping in the drain region, the n-type lightly doped drain (nLDD) device is commonly employed in integrated circuit microelectronics fabrications where low power dissipation is desired. The complementary type of FET is the pMOS device which employs p-type doped regions for source and drain in an n-type substrate. The pMOS device has somewhat lower current drive capability compared to the nMOS device, but has inherently lower drain leakage current.
Conventional FET device designs are often embellished with doped regions additional to the source and drain regions. Such regions are often formed adjacent to source and/or drain regions by ion implantation, and serve to modify or improve device characteristics. These additional doped regions are referred to as pocket regions, and may be either polarity depending on the particular device and purpose.
For many applications in microelectronics technology where drive current capability with low power dissipation is important, it is desirable to have an nMOS FET with very low drain leakage current. Methods of formation of drain junctions which have low reverse-bias current accomplish this objective, either by the inherent nature of the junction or by utilizing a compensating method such as a pocket region surrounding the drain region. Formation of pocket regions with conventional p-type dopants such as boron are not without problems, such as reverse short channel effects (RSCE), which limit the operation of the FET.
It is thus towards the goal of forming nLDD NMOSFET devices with low drain leakage current and power consumption and reduced reverse short channel effect that the present invention is particularly directed.
Various methods have been disclosed for forming pocket regions adjacent to source or drain regions in a FET device to modify device properties.
For example, Burr et al., in U.S. Pat. NO. 5,753,958, disclose a method for forming a FET with adjustable threshold voltage by employing a pocket region adjacent to source or drain of an FET to adjust the threshold voltage of the FET device. The method employs a voltage applied directly to the pocket region by means of a connection line thereto, and there may be applied a back bias to the device by the same means.
Further, Burr et al., in U.S. Pat. No. 5,780.912, disclose a method for forming a low threshold voltage FET device having an asymmetric threshold voltage. The method employs an implanted halo pocket region under and adjacent to source or drain region of the FET device.
Still further, Tsai et al., in U.S. Pat. No. 5,757,045, disclose a CMOS structure for forming a CMOS FET device with reduced susceptibility to punch-through. The structure employs a dual pocket regions implanted in the channel regions adjacent to source and drain regions.
Finally, Richards, Jr. et al., in U.S. Pat. No. 5,786,620, disclose a method for forming a Fermi-threshold FET device with significantly improved threshold voltage and performance. The method employs an implanted pocket region adjacent to the drain region of opposite conductivity type, which acts as a stop to the drain electric field and prevents drain—source reach-through, increasing short channel performance.
Desirable in the art of FET devices formed within microelectronics fabrications are additional methods for forming FET devices with low drain leakage current and low power consumption.
It is towards these goals that the present invention is generally directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method for forming a field transistor (FET) with attenuated drain leakage current.
A second object of the present invention is to provide a method for forming in accord with the first object of the present invention, an NMOS NLDD low power field effect transistor with attenuated power dissipation and drain leakage current without increased reverse short channel effect.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention where the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided a method for forming a field effect transistor (FET) with attenuated drain leakage current. To practice the invention, there is provided a silicon substrate within which are fabricated nMOS field effect transistors (FET) with lightly doped n-type drain regions (nLDD) employing arsenic (As) dopant atoms. There is then implanted indium (In) dopant atoms adjacent to the As diffused junction to form a p-type pocket therein. There is then avoided the customers high temperature rapid thermal annealing (RTA) step between 900 to 1050 degrees centigrade and instead employed a thermal annealing for 2 hours at 750 degrees centigrade, whereupon the implanted indium atoms undergo transient enhanced diffusion (TED) to form a graded junction profile, resulting in attenuated drain leakage current without increased reverse short channel effect (RSCE).
The present invention provides a method for forming a graded n-type pocket employing In as an ion implanted dopant wherein the transient enhanced diffusion (TED) of indium atoms during a thermal annealing step at 750 degrees centigrade forms a graded junction profile with low drain leakage current without increased reverse short channel effect (RSCE).
The present invention employs methods and materials as are well known in the art of microelectronics fabrication, but in a novel order and sequence. The method of the present invention is therefore readily commercially implemented.
REFERENCES:
patent: 5753958 (1998-05-01), Burr et al.
patent: 5757045 (1998-05-01), Tsai et al.
patent: 5780192 (1998-07-01), Burr et al.
patent: 5786620 (1998-07-01), Richards, Jr. et al.
patent: 5923987 (1999-07-01), Burr
Stanley Wolf Ph.D. and Richard N. Tauber Ph.D. in Silicon Processing for the VLSI Era, vol. 1: Process Technology, Lattice Press, 1986, pp. 27, 57-58.
Diaz Carlos H.
Lin Bi-Ling
Wang Jyh-Haur
Wu Chung-Cheng
Ackerman Stephen B.
Brewster William M.
Fahmy Wael
Saile George O.
Szecsy Alek P.
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