Drain extended MOS transistors with multiple capacitors and...

Details Drain extended MOS transistors with multiple capacitors and... Drain extended MOS transistors with multiple capacitors and...

2006-06-13

2006-06-13

Nguyen, Cuong (Department: 2811)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S957000

Reexamination Certificate

active

07060556

ABSTRACT:
Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate layer (16) and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductivity type in a semiconductor substrate (4). A second capacitor structure comprising a second dielectric layer (26) and a second gate layer (28) is formed overlying the first gate structure. A source region (22) of a second conductivity type formed in the semiconductor substrate (6) proximate the first lateral side of the gate and a drain extension region/well (12) lightly doped of the second conductivity type is formed in the semiconductor substrate under a portion of the gate structure. A drain region (24) of the second conductivity type formed within the drain extension region (12). The first capacitor structure and the second capacitor structure connect in series to permit a higher operational gate voltage. Other systems and methods are disclosed.

REFERENCES:
patent: 5296393 (1994-03-01), Smayling et al.
patent: 5604369 (1997-02-01), Duvvury et al.
patent: 6146939 (2000-11-01), Dasgupta
patent: 6548874 (2003-04-01), Morton et al.
patent: 6621128 (2003-09-01), Lee et al.
patent: 6660603 (2003-12-01), Mitros
patent: 6804095 (2004-10-01), Kunz et al.

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