Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-10-18
2003-11-04
Loke, Steven (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S157000, C438S269000, C438S158000, C257S347000
Reexamination Certificate
active
06642115
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to metal oxide semiconductor field effect transistors (MOSFETS) and more particularly to a double-gate MOSFET that has several advantages over conventional single-gate MOSFETs.
2. Description of the Related Art
It is conventionally known that a double-gate MOSFET has several advantages of over conventional single-gate MOSFET structures (dual-gates are side by side, while double-gates form a top and bottom gate structure). For example, the double-gate MOSFET structure has higher transconductance, lower parasitic capacitance and superior short-channel characteristics when compared to single-gate MOSFET structures. Various simulations have shown that a 30 nm channel double-gate MOSFET will show very high transconductance (2300 mS/mm) and very fast switching speeds. Moreover, good short-channel characteristics are obtained down to a 20 nm channel length, which does not require doping. Therefore, double-gate MOSFETs circumvent tunneling breakdown, and avoid the dopant quantization and impurity scattering associated with the conventional doping required in single-channel MOSFET structures.
However there is no conventional method of making a double-gate MOSFET structure which has both the top and bottom gate self-aligned to the source/drain suicides and which produces a planarized surface after the formation of the source/drain and gate structures. Conventional efforts to form a double-gate MOSFET structure generally fall into three categories.
One method etches silicon into a pillar structure and deposits gates around the pillar structure. However, with this method, it is difficult to form thin vertical pillars (e.g., 10 nm) that are free of reactive ion etching (RIE) damage and to maintain good thickness control.
Another method forms a conventional single-gate MOSFET and uses either selective epitaxy or bond-and-etch-back techniques to form the second gate. However, with this method, it is difficult to keep the top and bottom gate oxides at the same thickness and to align the gates with each other.
A third method begins with a thin SOI film, and patterns tunnels under the SOI film. Then, gate electrodes are deposited in the tunnel around the SOI film. However, this method also suffers silicon thickness control problems and gate alignment problems.
Therefore, there is a need for a method and structure of forming a double-gate MOSFET structure which provides a planarized surface after the formation of the source/drain and gate structures and which allows for the gate and source/drain suicides to be self-aligned.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for an integrated circuit having a first gate, a second gate, and source and drain regions adjacent the first and second gate wherein the first gate and the source and drain regions are silicided in a single self-aligned process. The integrated circuit has a channel region between the first gate and the second gate, conductors electrically connecting the first and the second gate, and an insulator above the first gate, and insulators between the channel region and the first gate and the second gate. The channel region includes channel extensions extending into the source and drain regions wherein the channel extensions have an arrow shape in cross-section.
The invention can also comprise a method for producing a double-gate metal oxide semiconductor field effect transistor which can form a laminated structure including forming a first sacrificial layer, forming a channel layer above the first sacrificial layer, and forming a second sacrificial layer above the channel layer. The method can also include removing the first sacrificial layer and the second sacrificial layer, depositing gate conductors around at least two sides of the channel layer, doping source and drain regions of the laminated structure, and forming an insulator between the channel layer and the first sacrificial layer and the second sacrificial layer. The method may also include forming conductors electrically connecting the gate conductors, forming source and drain regions adjacent the laminated structure, growing channel extensions into the source and drain regions, wherein the channel extensions have an arrow shape in cross-section. The removal of the first sacrificial layer and the second sacrificial layer leaves the channel layer as a bridge having open space above and below the channel layer.
REFERENCES:
patent: 5102819 (1992-04-01), Matsushita et al.
patent: 5120666 (1992-06-01), Gotou
patent: 5166084 (1992-11-01), Pfiester
patent: 5273921 (1993-12-01), Neudeck et al.
patent: 5371401 (1994-12-01), Kurita
patent: 5461250 (1995-10-01), Burghartz et al.
patent: 5497019 (1996-03-01), Mayer et al.
patent: 5646058 (1997-07-01), Taur et al.
patent: 5708286 (1998-01-01), Uesugi et al.
patent: 5773331 (1998-06-01), Solomon et al.
patent: 5923963 (1999-07-01), Yamanaka
patent: 6143582 (2000-11-01), Vu et al.
patent: 6346446 (2002-02-01), Ritenour
patent: 05-226655 (1993-09-01), None
Wong, et al., “Self-Aligned (Top and Bottom) Double-Gate MOSFET with a 25 nm Thick Silicon Channel”, Electron Devices Meeting, 1997, Technical Digest, International, 1997, pp. 427-430.
Lee, et al., Super Self-Aligned Double-Gate (SSDG) MOSFETs Utilizing Oxidation Rate Difference and Selective Epitaxy, IEDM, Dec. 5, 1999, IEEE 1999.
Su et al., “New Planar Self-Aligned Double-Gate Fully-Depleted P-MOSFET's Using Expitaxial Lateral Overgrowth (ELO) and Selectively Grown Source/Drain (S/D)”, 2000 IEEE International SOI Conference, Oct. 2000.
Cao et al., “0.18-um Fully-Depleted Silicon-on-Insulator MOSFET's”, IEEE Electron Device Letters, vol. 18, No. 6, Jun. 1997, pp. 251-253.
Cohen Guy M.
Wong Hon-Sum P.
August Casey P.
Gebremariam Samuel A
International Business Machines - Corporation
Loke Steven
McGinn & Gibb PLLC
LandOfFree
Double-gate FET with planarized surfaces and self-aligned... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Double-gate FET with planarized surfaces and self-aligned..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Double-gate FET with planarized surfaces and self-aligned... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3149586