Double SOI device with recess etch and epitaxy

Details Double SOI device with recess etch and epitaxy Double SOI device with recess etch and epitaxy

2001-02-20

2002-08-13

Ho, Hoai (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C257S347000

Reexamination Certificate

active

06432754

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and more particularly to a ground-plane SOI device that includes an oxide layer under the device channel region, located in an area between the deep source/drain regions. This oxide layer is butted against the shallow extensions (therefore, no shallow extension area junction capacitance exists) and is laterally adjacent to the deep source/drain regions (therefore, reduced source/drain perimeter junction capacitance is obtained). Additionally, the present invention also provides various methods of forming the aforementioned ground-plane SOI device in which the short channel effects typically present in such devices have been substantially eliminated.
BACKGROUND OF THE INVENTION
In semiconductor processing, SOI technology is becoming increasingly more important since it permits the formation of high-speed integrated circuits. In SOI technology, a relatively thin layer of semiconducting material, namely monocrystalline Si, overlays a layer of insulating material, e.g., a buried oxide region. This relatively thin layer of semiconducting material is generally the area wherein active devices such as field effect transistors (FETs) are formed in the SOI wafer. Devices formed on SOI offer many advantages over their bulk Si counterparts including higher performance, absence of latch-up, higher packing density and lower voltage applications.
Despite the advantages obtained using SOI technology, SOI technology suffers from short channel effects which are also present in bulk Si technology. As is known to those skilled in the art short channel effects tend to degrade the electronic integrity of the device and lead to unacceptable device leakage current known in the art as ‘off-current’. Short channel effects are more pronounced in very large scale integration (VSLI) devices wherein the channel length is less than 1 &mgr;m.
In view of the short channel effect problem mentioned above with prior art SOI devices, there is a continued need for developing a new and improved SOI device which substantially eliminates the short channel effects.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a ground-plane device that has no shallow extension junction capacitance while having reduced deep source/drain perimeter junction capacitance.
Another object of the present invention is to provide a ground-plane device in which the advantages of both ground-plane and SOI devices are achieved in a single device.
A further object of the present invention is to provide a ground-plane device which allows for a highly doped ground plane to be present without dopants diffusing up into the channel region of the device. As is known to those skilled in the art, the channel region is typically located beneath the field effect transistor, i.e., beneath the gate dielectric and gate conductor.
These and other objects and advantages are achieved in the present invention by providing a ground-plane SOI device having an oxide region present beneath the channel region, located in an area between the source/drain regions. This oxide region, which is butted against the shallow extensions, and is laterally adjacent to the deep source/drain regions, provides a device having no shallow extension area junction capacitance and reduced deep source/drain perimeter junction capacitance.
One aspect of the present invention relates to various methods of fabricating a ground-plane device having the above-mentioned characteristics. Specifically, a first method of the present invention comprises the steps of:
(a) forming a back oxide layer in a Si-containing layer of a silicon-on-insulator (SOI) wafer so as to separate said Si-containing layer into a top Si-containing layer and a bottom Si-containing layer, said SOI wafer having a buried oxide layer formed on a Si substrate and said Si-containing layer formed on said buried oxide layer;
(b) forming a ground-plane doping region into a top portion of said bottom Si-containing layer;
(c) forming a gate region on a portion of said top Si-containing layer, said gate region including a gate dielectric formed on said top Si-containing layer, a gate conductor formed on said gate dielectric and a hard mask formed on said gate conductor;
(d) forming halo and source/drain extension regions in said top Si-containing layer;
(e) forming spacers on a portion of said gate dielectric so as to protect vertical sidewalls of said gate conductor and said hard mask;
(f) removing all exposed portions of said top Si-containing layer so as to expose a portion of said back oxide layer underlying said top Si-containing layer;
(g) removing said exposed portions of said back oxide layer;
(h) forming source and drain regions in said bottom Si-containing layer; and
(i) forming salicide regions on all exposed silicon surfaces.
A second method of the present invention comprises the steps of:
(a) forming a back oxide layer in a Si-containing layer of a silicon-on-insulator (SOI) wafer so as to separate said Si-containing layer into a top Si-containing layer and a bottom Si-containing layer, said SOI wafer having a buried oxide layer formed on a Si substrate and said Si-containing layer formed on said buried oxide layer;
(b) forming a ground-plane doping region into a top portion of said bottom Si-containing layer;
(c) forming a gate region on a portion of said top Si-containing layer, said gate region including a gate dielectric formed on said top Si-containing layer, a gate conductor formed on said gate dielectric and a hard mask formed on said gate conductor;
(d) forming halo and source/drain extension regions in said top Si-containing layer;
(e) forming spacers on a portion of said gate dielectric so as to protect vertical sidewalls of said gate conductor and said hard mask;
(f) forming a contact to the bottom Si-containing layer by conducting a self-aligned ion implant step into regions next to the gate region and the spacers;
(g) forming source and drain regions in said bottom Si-containing layer; and
(h) saliciding all exposed silicon surfaces.
A third method of the present invention comprises the steps of:
(a) forming a damascene oxide layer on a-surface of a Si-containing layer of an SOI wafer, said SOI wafer including a Si substrate, a buried oxide layer and said Si-containing layer;
(b) providing an opening in said damascene oxide layer stopping on said Si-containing layer;
(c) forming a local back oxide region in said Si-containing layer through said opening;
(d) forming a local ground-plane region beneath said local back oxide region;
(e) forming a gate region including at least a gate dielectric and a gate conductor in said opening;
(f) removing said damascene oxide layer;
(g) forming source and drain regions in said Si-containing layer of said SOI wafer;
(h) forming extension and halo implant regions in said Si-containing layer above said local back oxide region;
(i) forming a conformal liner about said gate region; and
(j) salicidinig all exposed silicon surfaces.
Another aspect of the present invention relates to a ground-plane SOI device which comprises:
at least a field effect transistor formed on a top Si-containing surface of a silicon-on-insulator (SOI) wafer; and
an oxide region present beneath the field effect transistor, which is located in an area between source and drain regions that are formed in said SOI wafer, said oxide region is butted against shallow extensions formed in said SOI wafer, and is laterally adjacent to said source and drain regions.


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