Double-gate vertical MOSFET transistor and fabrication method

Details Double-gate vertical MOSFET transistor and fabrication method Double-gate vertical MOSFET transistor and fabrication method

2001-04-27

2004-09-07

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

C438S151000

Reexamination Certificate

active

06787402

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of MOSFET transistors and more particularly to a double-gate MOSFET transistor having separate gate electrodes and the associated fabrication method.
2. Description of the Background Art
As process geometries continue to shrink in the drive toward higher circuit density, the adverse consequences arising from short channel effects become increasingly important. Substantial attention is being directed toward the use of vertical channel MOSFET transistors. It will be appreciated that a MOSFET transistor may be fabricated, such as on an SOI wafer, in a vertical channel configuration, often characterized as a FinFET, by virtue of the vertical fin which defines the source-drain channel. It will be appreciated that FinFET transistors have a potential for use with sub-twenty-five nanometer (<25 nm) gate lengths as they can provide high drive current and high immunity to short-channel effects. However, the conventional fabrication practices utilized for creating these vertical MOSFET transistors only provide for the creation of single gate devices. One such FinFET device recently described is a MOSFET having a single gate structure distributed over opposing sides of the vertical “fin” channel.
The traditional use of single gate devices limits the gate biasing alternatives available for the associated device. A single gate device obviously requires that threshold voltage be controlled by utilizing a single gate control voltage. It will be appreciated, however, that a number of applications exist in which the use of more than one control voltage can provide a number of benefits.
Therefore, a need exists for a double-gate vertical MOSFET transistor having a pair of separate gates. The present invention satisfies that need, as well as others, and overcomes deficiencies of previously developed solutions.
BRIEF SUMMARY OF THE INVENTION
The present invention describes a double-gate vertical MOSFET transistor having separate gates and an associated method for fabricating the transistor. The vertical MOSFET is configured with a vertical channel extending from an insulated substrate, such as the insulator layer of an SOI wafer. The sidewalls of the vertical channel are insulated from the adjacent gates with a thin layer of gate insulation, while a thicker capping layer of insulation is provided over the top of the vertical channel. Separate gate electrodes are formed on each side of the vertical channel adjacent to the insulation on the sidewalls of the vertical channel. The conduction-state of the resultant vertical double-gate transistor is thereby responsive to the combination of applied gate voltages on either side of the vertical channel. It will be appreciated that the use of a double-gate device can simplify transistor biasing and be utilized in applications that do not lend themselves to the use of a single gate.
By way of example, the double-gate vertical MOSFET transistor of the present invention is generally fabricated according to the following steps. A layer of insulation, such as silicon nitride (Si
3
N
4
) is deposited over a thin silicon layer. The insulation and silicon layer are patterned to form a silicon-insulator stack having a silicon fin capped with insulation having opposing ends which are configured for receiving source and drain contacts. The channel preferably remains undoped having a threshold voltage of determined solely by the gate work function. The vertical surfaces of the silicon fin are insulated, such as by the formation of gate oxide, to isolate the vertical channel from subsequently created gates. Separate gate electrodes are then formed on opposing sides of the insulated silicon-insulator stack. Preferably, the separate electrodes are formed by depositing a thick layer of gate electrode material over the substrate and then polishing the electrode material until the insulator cap of the silicon-insulator stack protrudes through, and electrically separates, the electrode material into a gate “A ” and a gate “B” The separate gate areas are then patterned to provide the desired gate width along the side of the silicon-insulator stack and to configure each electrode with areas for receiving a contact. Conventional process steps may thereafter be utilized to form the contacts and complete the fabrication of the double-gate vertical MOSFET transistor.
An object of the invention is to create a double-gate vertical MOSFET transistor having separate gate electrodes.
Another object of the invention is to provide a fabrication method for a double-gate vertical MOSFET transistor.
Another object of the invention is to provide a double-gate vertical MOSFET transistor fabrication process that can be implemented on an SOI substrate.
Another object of the invention is to provide a double-gate vertical MOSFET transistor fabrication process in which an insulation capping layer is utilized above the vertical channel for separating the two separate gates of the device.
Another object of the invention is to provide a double-gate vertical MOSFET transistor fabrication process in which separate electrodes are formed by depositing gate electrode material over the substrate and polishing until the insulation layer protrudes.
Another object of the invention is to provide a double-gate vertical MOSFET transistor fabrication process that can utilize conventional semiconductor processing equipment.
Further objects and advantages of the invention will be brought out in the following portions of the specification, wherein the detailed description is for the purpose of fully disclosing preferred embodiments of the invention without placing limitations thereon.


REFERENCES:
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patent: 5382816 (1995-01-01), Mitsui
patent: 5689127 (1997-11-01), Chu et al.
patent: 6118161 (2000-09-01), Chapman et al.
patent: 6252284 (2001-06-01), Muller et al.
Xuejue Huang, Wen-Chin Lee, Charles Kuo, Digh Hisamoto, Leland Chang, Jakub Kedzierski, Erik Anderson, Hideki Takeuchi, Yang-Kyu Choi, Kazuya Asano, Vivek Subramanian, Tsu-Jae King, Jeffrey Bokor and Chenming Hu, “Sub 50-nm FinFET: PMOS”, 1999 IEDM, 4 pages.

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