Capping layer for reducing amorphous carbon contamination of...
Carrier mobility enhanced channel devices and method of...
Channel strain engineering in field-effect-transistor
Chemical vapor deposition of silicate high dielectric...
Circuit and method for a folded bit line memory cell with...
Cleaning solution and method for selectively removing layer...
CMOS compatible SOI process
Cmos gate architecture for integration of salicide process in su
Cmos of semiconductor device and method for manufacturing...
CMOS semiconductor device having dual-gate electrode constructio
CMOS structure including dual metal containing composite gates
Co-deposition of nitrogen and metal for metal silicide...
Cobalt silicidation using tungsten nitride capping layer
Cobalt silicide structure for improving gate oxide integrity...
Combined gate cap or digit line and spacer deposition using HDP
Composite spacer scheme with low overlapped parasitic...
Conductive layer forming method using etching mask with directio
Conductor layer nitridation
Conductor layer nitridation
Contact process using taper contact etching and polycide step