Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-01-13
2001-08-28
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S630000, C438S664000, C438S660000, C438S683000
Reexamination Certificate
active
06281102
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a silicide semiconductor structure. More specifically, the present invention relates to a cobalt silicide structure for use in processes having a minimum line width less than 0.25 microns.
2. Discussion of Related Art
As semiconductor processing techniques improve, the minimum feature size that can be produced by a semiconductor process decreases. Semiconductor processes are typically defined by minimum feature size (i.e., 0.5 micron process, 0.35 micron process, 0.25 micron process, 0.18 micron process). As the minimum feature size of semiconductor processes decreases, so does the width of the conductive elements formed by the process. As a result, the resistances of the conductive structures undesirably increase.
One example of a conductive element is a metal silicide structure, which is fabricated by reacting silicon with a refractory metal. Semiconductor processes having a minimum feature size of 0.25 microns or greater typically use titanium silicide (TiSi
2
). A titanium silicide structure is typically formed by depositing a layer of titanium over a layer of polycrystalline silicon and annealing the resulting structure. Titanium can be deposited over the polysilicon layer, even if there is a native oxide layer over the upper surface of the polysilicon layer, because the titanium will getter (i.e., remove) the native oxide layer. However, as the minimum feature size decreases below 0.25 microns, it becomes increasingly more difficult to maintain the low resistance of titanium silicide. Consequently, other elements have been used to replace the titanium.
One such element is cobalt. However, while cobalt silicide has a lower resistivity than titanium silicide when formed on small geometries, there are several problems associated with the use of cobalt to form a metal silicide structure. First, cobalt is incapable of gettering oxygen in the same manner as titanium. As a result, the upper surface of a polysilicon layer must be thoroughly cleaned prior to depositing cobalt. This cleaning adds to the complexity of the process. Any oxide left on top of the polysilicon layer can cause problems. For example, the cobalt can migrate to the areas where the native oxide does not exist, thereby resulting in the formation of cobalt silicide spikes that extend through the polysilicon layer to underlying gate oxide or silicon. If the cobalt silicide spikes reach an underlying gate oxide layer, undue stress is placed on the gate oxide layer, thereby causing the gate oxide to fail. If the cobalt silicide spikes reach an underlying silicon substrate, a short will exist between the metal silicide structure and the underlying substrate, thereby resulting in excessive leakage current. A thin titanium layer has been proposed between the cobalt layer and the polysilicon layer. (See, M. Lawrence, A. Dass, D. B. Fraser and C. S. Wei, “Growth of epitaxial CoSi
2
on (100) Si”, Appl. Phys. Lett., 58, pp. 1308-1310 (1991).
In addition, when the cobalt and polysilicon layer are annealed in the presence of oxygen, it is possible for the ambient oxygen to diffuse through the cobalt to the cobalt-polysilicon interface. Under these conditions, silicon oxide can be formed at the cobalt-polysilicon interface. The presence of silicon oxide at the cobalt-polysilicon interface can cause the same problems caused by the presence of native oxide on the upper surface of the polysilicon layer. Some conventional processes provide for a capping layer over the cobalt layer to prevent ambient oxygen from diffusing through the cobalt layer to the cobalt-polysilicon interface. One such process is described in U.S. Pat. No. 5,384,285 to Sitaram et al.
It would therefore be desirable to have a method for forming a cobalt silicide structure that solves the above-described problems.
SUMMARY
Accordingly, the present invention provides an improved method of fabricating a cobalt silicide structure that includes the steps of: (1) forming a silicon structure, wherein a native oxide is located over a first surface of the silicon structure, (2) loading the silicon structure into a chamber, (3) introducing a vacuum to the chamber, (4) depositing a titanium layer over the first surface of the silicon structure, wherein the thickness of the titanium layer is selected to remove substantially all of the native oxide, (5) depositing a cobalt layer over the titanium layer, (6) depositing an oxygen impervious cap layer over the cobalt layer; and then (7) breaking the vacuum in the chamber, and (8) subjecting the silicon structure, the titanium layer, the cobalt layer and the cap layer to an anneal, thereby forming the cobalt silicide structure. The cap layer can be, for example, titanium or titanium nitride.
The resulting cobalt silicide structure is substantially free from oxygen (i.e., oxide). Consequently, an underlying gate oxide or substrate is advantageously protected from the effects of cobalt silicide spiking.
The present invention will be more fully understood in view of the following description and drawings.
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Flinn, et al., “Measurement and Interpretation of Stress in Aluminum-Based Metallization as a Function of Thermal History,” IEEE Transactions on Electron Devices, 34th ed., p. 689-699, (Mar., 1987).
IInuma, et al., “Highly Uniform Heteroepitaxy of Cobalt Silicide by Using Co-Ti Alloy for Sub-quarter Micron Devices,” 1998 Symposium on VlSI Technology, p. 188-189, (1998).
Byun, et al., “Defect Generation during Epitaxial CoSi2 Formation Using Co/Ti Bilayer on Oxide Patterned (100)Si Substrate and Its Effect on the Electrical Properties,” J. Electrochem, Soc., vol. 143, No. 3, Mar. 1996, p. L56-L58.
Wang et al., “New CoSi2 Salicide Technology for 0.1 um Processes and Below,” 1995 Symposium on VLSI Technology, p. 17-18.
Dass, et al., “Gowth of epitaxial CoSi2 on (100) Si,” Appl. Phys. Lett, vol. 58, No. 12, Mar. 25, 1991, p. 1308-1310.
Alberti, et al., “Reaction and thermal stability of cobalt disilicide on polysilicon resulting from a Si/Ti/Co multilayer system,” J. Vac. Sci. Technol. B17(4), Jul./Aug. 1999, p. 1448-1455.
“High Conductivity Nickel Silicide Polycide Gates For Sub-Micron Field Effect Transistors”, IBM Technical Disclosure Bulletin; Dec. 1989.
Cao Wanqing
Lee Sang-Yun
Lee Shih-Ked
Lo Guo-Qiang
Bever Hoffman & Harms LLP
Integrated Device Technology Inc.
Lee Calvin
Smith Matthew
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