Channel strain engineering in field-effect-transistor

Details Channel strain engineering in field-effect-transistor Channel strain engineering in field-effect-transistor

2007-06-08

2010-11-30

Landau, Matthew C (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C257SE21294

Reexamination Certificate

active

07842592

ABSTRACT:
There is disclosed a method of applying stress to a channel region underneath a gate of a field-effect-transistor, which includes the gate, a source region, and a drain region. The method includes steps of embedding stressors in the source and drain regions of the FET; forming a stress liner covering the gate and the source and drain regions; removing a portion of the stress liner, the portion of the stress liner being located on top of the gate of the FET; removing at least a substantial portion of the gate of a first gate material and thus creating an opening therein; and filling the opening with a second gate material.

REFERENCES:
patent: 6225173 (2001-05-01), Yu
patent: 2006/0160317 (2006-07-01), Zhu et al.
patent: 2007/0090462 (2007-04-01), Wu et al.
patent: 2007/0096184 (2007-05-01), Akamatsu
patent: 2007/0126036 (2007-06-01), Ohta et al.
patent: 2007/0132038 (2007-06-01), Chong et al.

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