Contact process using taper contact etching and polycide step

Details Contact process using taper contact etching and polycide step Contact process using taper contact etching and polycide step

1997-04-28

1999-06-22

Quach, T. N.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438595, 438640, 438739, H01L 2128, H01L 21311

Patent

active

059151986

ABSTRACT:
A method and structure are disclosed related to tapered contact holes in VLSI and ULSI technologies. The contact hole is formed by taking advantage of two-tiered polycide lines formed with a step. The polycide lines with steps are further formed with oxide spacers. The resulting structure is then used to form contact hole in between the oxide spacers. Because the oxide spacers are used--without the need for a tightly toleranced mask--to delimit the area of the contact at the bottom of the hole, a larger area of contact is obtained in addition to the tapered edges that are formed. Polycide is chosen to be a multilayer structure comprising tungsten-silicide (WSi.sub.2) over poly-silicon (poly-Si). Next, polycide is patterned by etching with a recipe which etches the WSi.sub.2 faster than it etches the underlying poly-Si. The etching, therefore, results in a structure where the WSi.sub.2 forms a step over the poly-Si layer. A layer of TEOS oxide is then deposited over the step structure and etched, thus forming oxide spacers surrounding the step structure. A second layer of TEOS is deposited and etched forming contact holes with the desired, gentle slopes yielding at the same time wide contact area at the bottom of the hole with improved reliability.

REFERENCES:
patent: 5203957 (1993-04-01), Yoo et al.
patent: 5206187 (1993-04-01), Doan et al.
patent: 5316616 (1994-05-01), Nakamura et al.
patent: 5381046 (1995-01-01), Cederbaum et al.
patent: 5490901 (1996-02-01), Kim
patent: 5491100 (1996-02-01), Lee et al.
patent: 5670404 (1997-09-01), Dai
patent: 5698072 (1997-12-01), Fukuda
patent: 5750441 (1998-05-01), Figura et al.
patent: 5795820 (1998-08-01), Kepler
patent: 5795827 (1998-08-01), Liaw et al.
S. Wolf, "Silicon Processing for the VLSI Era" --vol. 2, Lattice Press, Sunset Beach, CA (1990), pp. 105, 536.

Affiliated with

Also associated with

Rating

Contact process using taper contact etching and polycide step does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Contact process using taper contact etching and polycide step, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Contact process using taper contact etching and polycide step will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1715400