Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-02-15
2002-08-13
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S299000, C438S303000, C438S652000, C438S683000
Reexamination Certificate
active
06432805
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor device fabrication, particularly to self-aligned silicide (salicide) technology.
BACKGROUND ART
As gate electrode lengths are scaled down, the source and drain junctions and polycrystalline silicon line width must also be scaled down. However, scaling down the source and drain junctions and polycrystalline line width increases parasitic resistance in the source and drain diffusion layers and the gate electrode, and also increases the sheet and contact resistance of the gate electrode and source/drain regions.
Salicide technology comprises forming metal silicide layers on the source/drain regions and/or on the gate electrode of a semiconductor device in a self-aligned manner. A conventional approach to reduce resistivity involves forming a multi-layered structure consisting of a low resistance refractory metal silicide layer on a doped polycrystalline silicon, typically referred to as a polycide. Salicide technology reduces parasitic, sheet and contact resistance in the source and drain diffusion layers and the gate electrode that results from scaling down the source and drain junctions and polycrystalline silicon line width.
Silicides are typically formed by reacting a metal with silicon (Si) within a specified temperature range for a specific period of time. Silicide layers may be self-aligned by different techniques. For example, the metal can be selectively deposited on the gate electrode and on the source/drain regions, with subsequent annealing to react the metal with underlying Si of the source/drain regions and the gate electrode to form the metal silicide layers. Alternatively, sidewall spacers, e.g., silicon nitride or silicon dioxide, are formed on the side surfaces of the gate electrode, followed by a blanket deposition of metal and annealing to react the metal with Si in the gate electrode and the source/drain regions, while the sidewall spacers prevent reaction with Si from the side surfaces of the gate electrode.
During annealing, the wafer is heated to a reaction temperature and held at the reaction temperature for a period of time sufficient for the metal layer to react with underlying Si to form a metal silicide layer on the source/drain regions and the gate electrode. Multiple annealing steps may be employed.
Various metals react with Si to form a metal silicide; however, titanium (Ti) and cobalt (Co) are currently the most common metals used to create metal silicides when manufacturing semiconductor devices utilizing salicide technology. Recently, attention has turned towards nickel (Ni) to form nickel silicide utilizing salicide technology. Nickel silicide avoids many limitations associated with TiSi
2
and CoSi
2
. Unlike Ti where Si diffuses into the metal layer when forming a Ti silicide, Ni, like Co, diffuses into Si, which helps to limit bridging between the metal silicide layer on the gate electrode and a metal silicide layer on the associated source/drain regions. The formation of nickel silicide requires less Si than TiSi
2
and CoSi
2
. Nickel silicide also exhibits almost no linewidth dependence on sheet resistance. Nickel silicide is normally annealed in a one step process, vis-a-vis a process requiring an anneal, an etch, and a second anneal, as occurs in TiSi
2
and CoSi
2
saliciding. In addition, nickel silicide exhibits lower film stress, i.e., causes less wafer distortion, than conventional Ti or Co silicides.
Salicide processing efficiency is improved through the use of sidewall spacers. Sidewall spacers allow a blanket layer of metal to be deposited over the wafer surface. Sidewall spacers typically comprise silicon dioxide or silicon nitride, but silicon nitride sidewall spacers are often preferable because silicon nitride is highly conformal and the sidewall spacers can be added and removed as needed throughout the manufacturing process. However, the use of silicon nitride sidewall spacers with salicide technology results in bridging between the metal silicide layer on the gate electrode and the metal silicide layers on associated source/drain regions, particularly when Ni is used.
There is a need for salicide technology that avoids bridging between the metal silicide layer on the gate electrode and the metal silicide layers on the source/drain regions when using silicon nitride sidewall spacers, particularly when implementing nickel salicide.
DISCLOSURE OF THE INVENTION
These and other needs are satisfied by embodiments of the present invention, which provide a method of salicide processing in semiconductor device fabrication, the method comprising depositing a refractory metal in the presence of nitrogen (N) on a wafer having a polysilicon gate electrode, source/drain regions, and silicon nitride sidewall spacers to form a metal nitride layer, suspending N flow, depositing the refractory metal over the metal nitride layer on the wafer, heating the wafer to react the refractory metal and Si to form a metal silicide layer on the polysilicon gate electrode and source/drain regions, and wet chemical stripping the unreacted metal and remaining metal nitride from the wafer. In an embodiment of the present invention, the refractory metals used to form the metal nitride and metal silicide layers include Ni, Co, Ti, platinum (Pt), tantalum (Ta) and tungsten (W).
A further aspect of the present invention relates to a semiconductor device that includes a polysilicon gate electrode, source/drain regions, and silicon nitride sidewall spacers, wherein a metal silicide layer is formed over the polysilicon gate electrode and source/drain regions without associated bridging between the metal silicide layer on the gate electrode and the metal silicide layers over the source/drain regions. In order to avoid bridging, a metal nitride layer is created by depositing a refractory metal, e.g., Co, Ti, Ta, Pt, Ni and W, on the wafer in the presence of N. Nitrogen flow is then suspended and the refractory metal is deposited over the metal nitride layer. A metal silicide layer, e.g., NiSi, is formed on the polysilicon gate electrode and source/drain regions by heating the wafer to react the refractory metal with available Si. Unreacted refractory metal and metal nitride are removed from the wafer by wet chemical stripping.
An advantage of the present invention is the ability to limit metal bonding with free Si in the silicon nitride sidewall spacers by initially depositing the refractory metal in the presence of N. The N bonds with free Si in the silicon nitride sidewall spacers, thereby removing such free Si so that it is not available to react with deposited metal and cause bridging between the metal silicide layer on the gate electrode and the metal silicide layers on associated source/drain regions.
The nitriding process also beneficially forms a mediating layer that prevents the deposited refractory metal from reacting with free Si, but allows the deposited metal to diffuse through the mediating layer during annealing to form the desired metal silicide layers on the gate electrode and source/drain regions. The metal nitride mediating layer thereby advantageously enables control of the metal silicide transformation rate.
Other advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.
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patent: 5970370 (1999-10-01), Besser et al.
patent: 6281102 (2001-08-01), Cao et al.
patent: 10294459 (1998-11-01), None
Hansen, Max,Constitution of Binary Alloys, 1038-1043,Genium Publising Corp, Schenectady, New York, 1985.
Gas, P., et al., “Kinetics of Formation of TM Silicide Thin Films: Self-Diffusion”,Properties of Metal Silicides, ed. Karen Maex and
Besser Paul R.
Ngo Minh Van
Paton Eric N.
Everhart Caridad
Lytle Craig P.
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