Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1998-11-05
2000-11-21
Niebling, John F.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438198, 438714, 438717, 438669, 438636, 438952, H01L 213205, H01C 214763
Patent
active
061502502
ABSTRACT:
An electrode material layer of a WSi.sub.2 /polysilicon lamination layer and a conductive material layer for antireflection made of TiN or TiON and containing the direction <200> are sequentially deposited on a gate insulating film. The conductive material layer is patterned through dry etching using a resist layer as a mask to leave a portion of the conductive material layer. The resist layer may be as thin as capable of patterning the conductive material layer. After the resist layer is removed, the electrode material layer is patterned through dry etching using the conductive material layer as a mask to leave a portion of the electrode material layer. A lamination of the left electrode material layer and conductive material layer is used as a gate electrode layer. A lamination of the resist layer and conductive material layer may be used as a mask.
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Hibino Satoshi
Tabara Suguru
Hack Jonathan
Niebling John F.
Yamaha Corporation
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