Combined gate cap or digit line and spacer deposition using HDP

Details Combined gate cap or digit line and spacer deposition using HDP Combined gate cap or digit line and spacer deposition using HDP

2002-12-16

2004-06-29

Cuneo, Kamand (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S778000, C438S788000, C438S792000, C427S574000, C427S569000

Reexamination Certificate

active

06756293

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to a method for fabricating integrated circuits. More particularly, the invention relates to a high density plasma process for forming insulating caps and sidewall spacers for word line gate electrodes and interconnects.
BACKGROUND OF THE INVENTION
In the manufacture of integrated circuits, both field-effect transistor gate electrodes and gate electrode interconnects are typically etched from a conductive layer that blankets the in-process circuitry. In semiconductor memory circuits, word lines formed from a uniformly-thick conductive layer which blankets the circuitry form both gate electrodes and gate interconnects. Where a word line passes over a field oxide region, it functions as a gate electrode interconnect; where it passes over a gate dielectric layer that overlies an active area, it functions as a gate electrode. In typical memory circuits, processor circuits and logic circuits, multiple gate electrodes are series coupled by intervening gate interconnects.
FIG. 1
depicts a conventional word line stack
10
of a memory circuit. The word line stack or “gate stack”
10
overlies a silicon substrate
15
, which is a small portion of a silicon wafer. Polysilicon layer
11
of word line stack
10
is insulated from the substrate
15
by a gate oxide layer
16
. The stack includes a polycrystalline silicon layer
11
and a low resistance metal silicide layer
12
. A silicide is a binary compound formed by the reaction of a metal, such as tungston, and silicon at elevated temperature. Also shown in
FIG. 1
is a silicon dioxide or silicon nitride capping layer
14
.
A typical process for fabricating a word line stack is to grow a gate oxide layer
16
on a lightly-doped silicon substrate
15
. Silicon substrate
15
is isolated into active region
17
by field oxide regions
18
, as shown in FIG.
1
. LOCal Oxidation of Silicon (LOCOS), shallow trench isolation (STI) or other field isolation techniques known in the art are used to provide oxide regions
18
for patterning silicon substrate
15
into active region
17
. After isolation of active region
17
, gate stack
10
, which includes polycrystalline silicon
11
and an overlying silicide layer
12
such as tungsten silicide or other highly conductive materials, and an insulating cap
14
of SiO
2
or Si
3
N
4
, are formed by blanket deposition and photolithography. Patterned photoresist is used as an etch mask in forming gate stack
10
and insulating cap
14
. In
FIG. 1
, the patterned photoresist has been removed. Chemical vapor deposition (CVD) of silicon oxide or nitride then provides an insulative spacer layer
19
, typically having a thickness in the range of about 200 to 2000 angstroms depending upon device geometry. Spacer layer
19
is next etched with an anisotropic etch, to form a set of sidewall spacers
19
for gate stack
10
. Remaining spacer layer
19
coats the sides of the gate stack
10
, as shown in FIG.
2
.
The conventional process flow for both word line stacks and digit lines therefore requires a capping layer deposition and etch, followed by a separate spacer deposition and etch. What is needed is a process flow requiring fewer fabrication steps for formation of cap
14
and spacer
19
, and which also provides the ability to independently tailor the thicknesses and shapes of the caps and spacers for particular semiconductor design applications.
SUMMARY OF THE INVENTION
The present invention provides a method for fabricating gate electrodes and gate interconnects which include protective silicon oxide or silicon nitride caps and spacers. A SiO
2
or Si
3
N
4
film is formed by a high density plasma chemical vapor deposition (HDPCVD) process.
A gate stack or digit line is first blanket deposited and etched, prior to forming a capping layer. Silicon oxide or silicon nitride is then deposited by HDPCVD to simultaneously form a cap and sidewall film of silicon oxide or silicon nitride. The film is deposited in a reaction zone of a high density plasma reactor while applying two or more selected substrate bias powers, source powers and/or gas mixtures, which advantageously permits tailoring the shape and thickness of the film for desired applications. In one preferred embodiment, a low bias power of below 500 Watts is provided in a first stage HDPCVD and the bias power is then increased to between 500 and 3000 Watts for a second stage HDPCVD to fabricate thin sidewall spacers, for enhanced semiconductor device density, and a relatively thick cap, as shown in FIG.
6
.
In an alternative embodiment, a gate stack and/or digit line is blanket deposited and etched, and a conventional capping layer and sidewall spacers are then deposited. Subsequently, silicon oxide or nitride is deposited by HDPCVD by the process of the invention including two or more bias and/or source powers and/or gas mixtures to produce a silicon oxide or nitride layer that is relatively thin on vertical surfaces and thicker on horizontal surfaces as shown in FIG.
8
. By doing so, the space between the stacks and spacers (x) is increased for the same undoped oxide or barrier thickness (b) at the horizontal surface at the bottom. See FIG.
8
. The space between the stacks is then filled with a suitable dielectric such as BPSG.
Preferred embodiments of the invention are described below with reference to the following accompanying drawings.


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