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Test circuit for reducing test time in semiconductor memory...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Test circuit for semiconductor device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Test circuit for semiconductor device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuit for semiconductor device with multiple memory...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Test circuit for semiconductor integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuit for testing a synchronous memory circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Test circuit method and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuit of semiconductor integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Test circuit of semiconductor memory

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Test circuit provided with built-in self test function

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuit topology reconfiguration and utilization...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuit, integrated circuit, and test method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuitry for determining the defect density of a semicondu

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuits for testing inter-device FPGA links including...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuits of semiconductor memory device for multi-chip...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test clock generation for higher-speed testing of a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test clocking scheme

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Test compaction using linear-matrix driven scan chains

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test component and method of operation thereof

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test configuration and method for testing a digital...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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