Test circuitry for determining the defect density of a semicondu

Details Test circuitry for determining the defect density of a semicondu Test circuitry for determining the defect density of a semicondu

1998-04-21

2000-05-09

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128

Patent

active

060618140

ABSTRACT:
A test structure according to the present invention provides a technique for determining defects as a function of metal layers. The technique is implemented by dividing the test structure into individual test blocks that correspond to certain metal layers. In the disclosed embodiment, for example, a test structure formed by a semiconductor process utilizing three layers of interconnect metal includes three distinct test blocks having similar or identical underlying test logic. In a first test block, the underlying test logic is predominantly connected by the first metal layer. In a second test block, the underlying test logic is predominantly connected by the second metal layer. In a third test block, the underlying test logic is primarily connected by the third metal layer. During the testing stage, test patterns are applied to each test block and the results are tabulated. Faults detected in a test block are allocated to the metal layer(s) corresponding to the predominant metal routing layer of the test block. Because the test logic is the same, faults due to the underlying test logic or transistors comprising the test logic can be discounted. In this manner, the test results of the different test blocks can be compared and problems with a specific metal or via layer are readily identified. In one embodiment of the invention, the test structure is located on a production die. In another embodiment, the test structure is located on a test die.

REFERENCES:
patent: 4486705 (1984-12-01), Stopper
patent: 5068547 (1991-11-01), Gascoyne
patent: 5479109 (1995-12-01), Lau et al.
patent: 5486786 (1996-01-01), Lee
patent: 5663967 (1997-09-01), Lindberg et al.
patent: 5724251 (1998-03-01), Heavlin
patent: 5905383 (1999-05-01), Frisch
LSI Logic Corporation, "Process Monitor (PROCMON) Cell", Feb. 1997, pp. 1-12, DB06-000042-05, Copyright .COPYRGT. 1995, 1996 & 1997.

Affiliated with

Also associated with

Rating

Test circuitry for determining the defect density of a semicondu does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test circuitry for determining the defect density of a semicondu, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test circuitry for determining the defect density of a semicondu will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1075740