Test clocking scheme

Details Test clocking scheme Test clocking scheme

2004-10-28

2008-10-28

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S731000, C714S744000, C365S201000

Reexamination Certificate

active

07444560

ABSTRACT:
A test clocking scheme that separates the clock driving the functional logic and the memory from the clock driving the test logic and the memory. In other words, the test clocking scheme separates the memory functional clock from the memory test clock into two clock paths. The test clocking scheme provides for the ability to separately shut off either the memory functional clock source or the memory test clock source, provides that less power is required during production testing, and provides that simulation time is reduced during design verification because the functional logic is not clocked.

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“Independent clocks for peripheral modules in system-on-chip design” by Watn et al. This paper appears in: SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip] Publication Date: Sep. 17-20, 2003 On pp. 25-28 ISBN: 0-7803-8182-3 INSPEC Accession No. 7823551.

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