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Lab-on-chip system and method and apparatus for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Lab-on-chip system and method and apparatus for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Lane testing with variable mapping

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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Language processing system which generates debugging source file

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Language-driven interface for an automated testing framework

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Large-scale cluster monitoring system, and method of...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Large-scale integrated circuit and method for testing a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Last-in first-out data stacks and processing data using such...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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Latch and phase synchronization circuit using same

Error detection/correction and fault detection/recovery – Pulse or data error handling – Skew detection correction
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Latent error detection

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Latent fault detector

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Latent fault detector

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Launch-on-shift support for on-chip-clocking

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Layered decoding approach for low density parity check...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Layered decoding of low density parity check (LDPC) codes

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Layered low density parity check decoding for digital...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Layered multiple description coding

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Layered multiple description coding

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Layered multiple description coding

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Layout for a semiconductor memory device having redundant elemen

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Patent

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