Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2005-08-09
2005-08-09
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S724000, C714S025000, C365S051000, C365S063000
Reexamination Certificate
active
06928596
ABSTRACT:
A test code is input to a test mode control circuit so that the test mode control circuit creates the test decode signal. The test decode signal is converted into serial data with a parallel·serial converting circuit in synchronization with a base clock. The serial data is input to a serial·parallel converting circuit located in the vicinity of the test code latch circuit dispersed on the semiconductor chip via one very long serial data line extending from end to end of the semiconductor chip.
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Hisada Toshiki
Kimura Tohru
Hogan & Hartson LLP
Lamarre Guy J.
Trimmings John P.
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