Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-07-21
2004-05-25
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S076680, C324S076590
Reexamination Certificate
active
06742153
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a test configuration and a method for testing a digital electronic filter.
As integrated digital circuits become increasingly complex, it is becoming more and more difficult to test the circuits as completely as possible with a reasonable level of expenditure. So-called self-test configurations referred to as BISTs (Built-In Self-Tests) are known. They not only permit good test results to be attained, but also provide a possibility for checking the circuit in situ outside the production process without testers. In that context, an additional circuit is used to excite the circuit which is to be tested in such a way that a high level of fault coverage is thus achieved. Since that procedure is deterministic, the reaction of the circuit to be tested has thus been determined from the beginning and can therefore be checked by using comparison values. If the expected reaction is obtained, then the circuit is in order.
That requires a large number of different input signals to be provided in order to create the prerequisite for finding as many faults as possible. However, it would mean that a test pattern generator would be necessary, which would naturally be associated with an unwanted level of expenditure.
Patent Abstracts of Japan, E-212, Nov. 24, 1983, Volume 7, No. 264, JP 58-145217 A shows a test configuration for a digital filter, in which a selection device is provided to forward data to a processing circuit during the test mode. A filter output signal which has been processed further is supplied to a CPU for fault evaluation purposes. The CPU also supplies the test data.
A publication entitled “Schaltungstest mit Boundary-Scan” [Circuit Test With Boundary Scan], by Auer and Kimmelmann, Heidelberg, Germany, published by Hüthig-Verlag, 1996, pages 6 to 13 describes an application, for testing purposes, of test patterns to inputs of a circuit in order to test the reaction of the circuit. In that context, the expected reaction is compared with the actual one. Pseudo-random test patterns are produced by using shift registers with feedback and are used as test pattern generators.
U.S. Pat. No. 5,754,455 shows a digital filter having a bit-serial architecture. Flipflops contained in the filter are reset to defined states for testing purposes.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a test configuration and a method for testing a digital electronic filter, which overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and which can be used to produce a large number of test patterns while still keeping a low level of circuit and control complexity required therefor.
With the foregoing and other objects in view there is provided, in accordance with the invention, a test configuration for a digital electronic filter having an input and an output, comprising an evaluation circuit connected to the output of the filter; and a multiplexer to be toggled or switched over between an operating mode and a test mode, the multiplexer feeding back the output of the filter to the input of the filter in the test mode, for applying a digital output signal from the output of the filter to the input of the filter as a test signal.
With the objects of the invention in view, there is also provided a method for testing a digital filter having an input and an output, which comprises applying a test signal to the filter in a test mode; feeding back at least a response signal to the input as the next test signal; comparing an output signal from the filter with a reference signal in the test mode; and applying a different signal to the filter in an operating mode.
The advantage of the invention is that a relatively high level of test coverage is achieved with just a very simple initial input signal. This is because the filter itself uses the simple input signal to produce a more complex response which can be compared, in any test pass, with inherently known nominal values, that can easily be compared with calculated nominal values.
The invention enables test patterns for a deterministic test to be produced with a very low level of circuit complexity, and additionally enables these test patterns to be laid out to be efficient, i.e. with a short transit time and a high level of fault detection.
In accordance with another feature of the invention, the output of the filter is fed back to the input through a serial line.
In accordance with a further feature of the invention, particularly good and economical developments are achieved by placing a parallel decimation filter at the input. A bit-serial filter which is connected downstream of the decimation filter has an output fed back to the input of the decimation filter.
In accordance with an added feature of the invention, in order to be able to change quickly and easily from the operating mode to the test mode, a changeover switch can be used to connect either a signal which is to be filtered or the fed-back signal to the filter as alternatives.
In accordance with an additional feature of the invention, in principle, very good test results can be attained as a result of applying a unit step as the first test signal, which can easily be achieved by fixing the filter input at logic
1
. This is not only very simple to implement, but also the filter needs to calculate the step response from this, and even that results in a relatively high level of test coverage if the individual calculated data words are compared with their nominal value.
In accordance with yet another feature of the invention, the fed-back signal is altered in the feedback path, with scrambling preferably being carried out. This allows even more faults to be detected.
In accordance with a concomitant feature of the invention, “white noise” is used as the input signal. This can be produced by using a pseudo-random generator, for example.
A signal equivalent to “white noise” is preferably obtained by coupling the output signal from the filter to the decimation filter in bit-serial form as the input signal. The constantly and very irregularly changing data in a bit-serial datastream has the same effect as the “white noise source” known from theory.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a test configuration and a method for testing a digital electronic filter, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
REFERENCES:
patent: 4305076 (1981-12-01), Lepere et al.
patent: 5504756 (1996-04-01), Kim et al.
patent: 5754455 (1998-05-01), Baker et al.
patent: 6014554 (2000-01-01), Smith
patent: 6470312 (2002-10-01), Suzuki et al.
patent: 2003/0028372 (2003-02-01), McArthur et al.
patent: 58-145 127 (1983-08-01), None
Council, C. et al.: “Self-Test For F.I.R. Filters”, Oct. 28, 1992, pp. 51-60, XP-002180895.*
A. Auer et al.: “Schaltungstest mit Boundary Scan” [test circuit with boundary scan], Hüthig Verlag, Heidelberg, 1996, pp. 6-13 (No in English).
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
Tu Christine T.
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