Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1998-10-07
2001-10-09
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S733000
Reexamination Certificate
active
06301678
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a configuration for reducing a test time required in a semiconductor memory device having a plurality of data input/output terminals.
2. Description of the Background Art
FIG. 11
shows a pin arrangement in a conventional semiconductor memory device
9000
. In
FIG. 11
, a reference character Q represents a pin. Each of pins Q represents an address pin, a data pin, a control signal pin, or one of a plurality of data I/O pins.
In a semiconductor memory device (especially SRAM as semiconductor memory device
9000
, all data input/output pins must be used in order to test its internal operation. If there is 36 data input/output pins, for example, data must be written into and read out from all of 36 data input/output pins and signals output from corresponding pads must be measured.
Especially when the number of I/O pins increases, as signal application and output measurement is required for all I/O pins, the configuration of a testing apparatus (probe) becomes complicated. In addition, with a large number of I/O pins, the number of chips (semiconductor memory devices) which can be measured at one time is limited. Thus, a simultaneous testing of a large number of chips is not allowed, which leads to a long test time and a large test cost.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor memory device allowing reduced test time and test cost saving by simplifying a test.
In one aspect of the present invention, a semiconductor memory device includes a plurality of data input/output pins; a plurality of memory cells transmitting and receiving a signal to and from a respective one of the plurality of data input/output pins; a plurality of control pins receiving a signal controlling an internal operation; a test signal generation circuit responsive to a signal supplied from the plurality of control pins, detecting a specific test mode and generating a corresponding test signal; and a test circuit responsive to a signal supplied as an input from a specific data input/output pin among the plurality of data input/output pins, testing operations of the plurality of memory cells based on the test signal, and externally providing as an output a test result from the specific data input/output pin, wherein the specific data input/output pin is lined up with the plurality of control pins.
One advantage of the present invention is that even in a semiconductor memory device having a large number of data input/output pins, a memory cell operation test can be conducted using a small number of specific data input/output pins (i.e. reduced I/O pin). Particularly lined up arrangement (collective arrangement) of the control pins and the specific data input/output pin simplifies signal application, and hence allows the operation test for all memory cells without necessitating a complicated testing apparatus. In addition, adjacent chips on a wafer can be tested at one time. Thus time and cost required for a test can be reduced.
Particularly, the memory cell operation test is readily allowed using a specific data input/output pin lined up with control pins no matter on which side the plurality of data input/output pins are arranged.
Further, the memory cell operation test is readily allowed, particularly by lining the specific data input/output pins with lines of control pins arranged in parallel, regardless of the position in which the plurality of data input/output pins are arranged.
More particularly, the specific data input/output pin is arranged at the end of the line of control pins. Hence, simple test signal input and test result measurement are allowed in a test mode (i.e. I/O reduction mode).
Particularly in the test mode (I/O reduction mode), a signal on the specific data input/output pin is used instead of the signals on all data input/output pins. Therefore signal input to all data input/output pins is not necessary. In addition, in the test mode a signal, which indicates a state of the memory cell, is provided from the specific data input/output pin as an output. Therefore the test can be conducted using the specific data input/output pin alone.
Even in a semiconductor memory device having a continuous multi bit write/erase function, reduced test time and test cost can be achieved as well.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5600606 (1997-02-01), Rao
patent: 5925141 (1999-07-01), Ariki
patent: 5950219 (1999-09-01), Rao
patent: 5965902 (1999-10-01), Beffa
patent: 5998869 (1999-12-01), Lin et al.
patent: 04-307751 (1992-10-01), None
patent: 06-208800 (1994-07-01), None
patent: 09-091998 (1997-04-01), None
Ohbayashi Shigeki
Sato Hirotoshi
Wada Tomohisa
De'cady Albert
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Ton David
LandOfFree
Test circuit for reducing test time in semiconductor memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Test circuit for reducing test time in semiconductor memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test circuit for reducing test time in semiconductor memory... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2599128