Test circuit for semiconductor device with multiple memory...

Details Test circuit for semiconductor device with multiple memory... Test circuit for semiconductor device with multiple memory...

1999-12-15

2003-02-04

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S718000, C714S733000

Reexamination Certificate

active

06516430

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a plurality of memory circuits and a memory test circuit mounted on the same chip, and to a recording medium on which data for preparing such a semiconductor device is recorded.
Semiconductor devices (LSIs) developed in recent years, such as ASICs, tend to have both logic circuits and a plurality of memory circuits mounted on a single chip.
Such a semiconductor device can achieve a higher data transfer rate (data transfer amount per unit time) between the logic circuits and the memory circuits, compared with that of a conventional semiconductor device. Further, such a semiconductor device requires no input/output circuits between the logic circuits and the memory circuits, and thus can achieve a reduction in the total power consumption, compared with a semiconductor device mounted with logic circuits and connected to a semiconductor device mounted with memory circuits.
A semiconductor device is subjected to an operation test prior to shipment to determine if the logic circuits and the memory circuits operate normally. That is, a semiconductor device is connected to a testing apparatus, and is operated in accordance with test signals supplied from the testing apparatus. The testing apparatus determines whether the semiconductor device is normal or not using the output signals of the semiconductor device.
As is well known, the memory circuits are subject, due to their structure, to memory cell defects and malfunctions caused, for example, by interference between memory cells. Therefore, it is required that the operation of the memory circuits alone be tested before that of the logic circuits. However, since the input/output terminals of the memory circuits are connected to the logic circuits, it is difficult to perform input/output operations with the memory circuits from outside the semiconductor device, because to do so requires pads for performing input/output operations with the memory circuits, and hence leads to an increase in the chip area of the semiconductor device.
To solve this problem, it has been considered to mount memory test circuits on a semiconductor device. However, as semiconductor devices become more and more multi-functional, the number of memory circuits mounted on a semiconductor device has increased, and if memory test circuits are mounted so as to correspond to the memory circuits on a one-to-one basis, the area occupied by the test circuits increases dramatically, thereby increasing the chip area and the cost of the semiconductor device. Thus, a test technique in which a plurality of memory circuits are tested using a smaller number of test circuits than the number of memory circuits is advantageous.
FIG. 1
is a schematic block diagram of a first conventional semiconductor device
1
. The semiconductor device
1
includes a memory circuit
2
and a test circuit
3
, which are formed on one chip together with logic circuits (not shown).
The memory circuit
2
has an input/output interface whose construction is analogous to that of an SDRAM (Synchronous Dynamic Random Access Memory). The test circuit
3
generates a control signal CMD, an address signal ADD, an operating clock signal CLK, and a data signal DATA, and outputs these signals to the memory circuit
2
.
The memory circuit
2
receives the control signal CMD in synchronism with the clock signal CLK, and operates in a mode based on this control signal CMD. In the write mode, the memory circuit
2
receives an address signal ADD and a data signal DATA in synchronism with the clock signal CLK, and stores the data signal DATA in a cell whose address corresponds to the address signal ADD as cell information. In the read mode, the memory circuit
2
receives an address signal ADD in synchronism with the clock signal CLK, reads cell information stored in the cell whose address corresponds to the address signal ADD, and outputs the read information as a data signal DATA.
The test circuit
3
generates an expected value, compares the expected value with the value of the data signal DATA provided from the memory circuit
2
, and outputs a determination signal DTRM generated based on the comparison result to a testing apparatus (not shown).
FIG. 2
is a schematic block diagram of a second conventional semiconductor device
4
. The semiconductor device
4
includes a plurality (two in this example) of memory circuits
5
a
and
5
b
, and two test circuits
6
a
and
6
b
corresponding to the memory circuits
5
a
,
5
b
, respectively. The circuits
5
a
,
5
b
,
6
a
and
6
b
are formed on one chip together with logic circuits (not shown).
The test circuits
6
a
and
6
b
operate like the aforesaid test circuit
3
. That is, the test circuit
6
a
applies to the memory circuit
5
a
a control signal CMD-
1
, an address signal ADD-
1
, a clock signal CLK-
1
, and a data signal DATA-
1
. The test circuit
6
a
compares the value of the data signal DATA-
1
received from the memory circuit
5
a
with an expected value, and outputs a determination signal DTRM-
1
based on the comparison result to a testing apparatus (not shown).
Further, the test circuit
6
b
applies to the memory circuit
5
b
a control signal CMD-
2
, an address signal ADD-
2
, a clock signal CLK-
2
, and a data signal DATA-
2
. The test circuit
6
b
compares the value of the data signal DATA-
2
received from the memory circuit
5
b
with an expected value, and outputs a determination signal DTRM-
2
based on the comparison result to the testing apparatus (not shown).
When the test circuits are mounted on the semiconductor device so as to correspond to the memory circuits on a one-to-one basis as described above, the chip area of the semiconductor device is dramatically increased. To overcome this problem, a method by which the operation of a plurality of memory circuits are tested using a single test circuit would be desirable. A third conventional semiconductor
7
device based on such a method is shown in FIG.
3
.
The semiconductor device
7
includes a plurality (two in this example) of memory circuits
8
a
and
8
b
, and a test circuit
9
. The circuits
8
a
,
8
b
and
9
are formed on one chip together with logic circuits (not shown).
The test circuit
9
tests the operation of the memory circuits
8
a
and
8
b
simultaneously. The reason is that when the memory circuits
8
a
and
8
b
are tested separately, it takes a lot of time, which leads to an increase in the cost of the semiconductor device
7
.
The test circuit
9
applies to the memory circuit
8
a
a control signal CMD, an address signal ADD, and a clock signal CLK, each of which is generated to be used by the memory circuits
8
a
and
8
b
in common. Further, the test circuit
9
applies data signals DATA-
1
and DATA-
2
, which are generated to be used individually, to the memory circuits
8
a
and
8
b
, respectively. This is because each of the memory circuits
8
a
and
8
b
uses a single terminal for both inputting and outputting data signals. If memory circuits, each having separate input and output terminals for transferring data signals, are used, a single data signal may be generated so that the memory circuits
8
a
and
8
b
can share such signal.
The test circuit
9
outputs to the testing apparatus (not shown) a determination signal DTRM having the result of a comparison made between the value of the data signal DATA-
1
received from the memory circuit
8
a
and an expected value and the result of a comparison made between the value of the data signal DATA-
2
received from the memory circuit
8
b
and the expected value. Thus, by using a single test circuit
9
to simultaneously test the two memory circuits
8
a
and
8
b
, the semiconductor device
7
prevents its chip area and testing time from increasing.
However, the third conventional the semiconductor device
7
encounters a problem concerning the distance between the test circuit
9
and each of the memory circuits
8
a
and
8
b
. That is, the wire l

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