Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-07-24
2007-07-24
Britt, Cynthia (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
10400452
ABSTRACT:
A semiconductor test circuit including an input terminal, a controller, a setting circuit, a command generator, a transmission path switching circuit and a comparator. The input terminal receives serial data including a command code and control data. The controller receives a control signal from the input terminal and outputs an internal control signal. The setting circuit receives serial data from the input terminal and outputs it to the command generator in response to the internal control signal. The command generator then generates an interface signal based on this serial data. The switching circuit receives the signal from one of its ports and outputs the received signal to another port in response to the internal control signal and the command code, and the comparator compares the interface signal received from the command generator with the signal received from the switching circuit.
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patent: 6587979 (2003-07-01), Kraus et al.
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patent: 6754863 (2004-06-01), Grannis, III
patent: 6763485 (2004-07-01), Whetsel
patent: 10-199294 (1998-07-01), None
Fukuyama Hiroyuki
Tanaka Hitoshi
Yonaga Takeru
Britt Cynthia
Oki Electric Industry Co. Ltd.
Rabin & Berdo PC
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