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I/O based column redundancy for virtual ground with 2-bit...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate

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I/O compression circuit for a semiconductor memory device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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I/O configuration and reconfiguration trigger through...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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I/O control apparatus having check recovery function

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent

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I/O device fault processing method for use in virtual...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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I/O device switching method

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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I/O device testing method and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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I/O handling for a multiprocessor computer system

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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I/O stress test

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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I/O switches and serializer for each parallel scan register

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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I2C bus protocol controller with fault tolerance

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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I2C test single chip

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Ibist identification loopback scheme

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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IBIST interconnect and bridge fault detection scheme

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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IBIST test for synchronous lines at multiple frequencies

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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IC chip tester using compressed digital test data and a method f

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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IC functional and delay fault testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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IC input memory with dual data and dual control inputs

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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IC measuring device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Skew detection correction
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IC multiplexer control circuitry for tap selection circuitry

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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