Test circuit of semiconductor memory

Details Test circuit of semiconductor memory Test circuit of semiconductor memory

2000-09-26

2003-10-14

Beausoliel, Robert (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C257S001000, C710S052000, C711S170000, C324S765010

Reexamination Certificate

active

06634002

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a test circuit in which a wafer test is performed for a semiconductor memory by using an external clock signal having a pulse repetition period longer than that of a clock signal actually used in a normal operation of the semiconductor memory.
2. Description of Related Art
A test circuit is generally used for a wafer test of a semiconductor integrated circuit such as a semiconductor memory or the like. In the test circuit, a low frequency clock signal having a pulse repetition period longer than that of a clock signal, which is actually used to perform a normal operation of the semiconductor integrated circuit, is used. Therefore, an operational performance of the semiconductor integrated circuit is tested by using the external clock signal having a pulse repetition period longer than that of a clock signal actually used in a normal operation of the semiconductor integrated circuit. A conventional test circuit of a synchronous dynamic random access memory (SDRAM) representing a semiconductor memory is described with reference to FIG.
8
and FIG.
9
.
FIG. 8
is a block diagram of an SDRAM having a conventional test circuit. In
FIG. 8
,
80
indicates an SDRAM.
81
indicates a conventional test circuit of the SDRAM
80
.
82
indicates a flip-flop of the conventional test circuit
81
. In the flip-flop
82
, an internal write command signal is produced from an external write command signal and an external clock signal.
83
indicates a flip-flop of the conventional test circuit
81
. In the flip-flop
83
, an internal pre-charge command signal is produced from an external pre-charge command signal and the external clock signal.
84
indicates a memory cell array of the SDRAM
80
. In the memory cell array
84
, an operation test is performed in a write recovery time-period determined by both the internal write command signal produced in the flip-flop
82
and the internal pre-charge command signal produced in the flip-flop
83
.
A wafer test operation of the SDRAM
80
performed by the conventional test circuit
81
is described.
FIG. 9
is a timing chart showing an operation of the conventional test circuit
81
. As shown in
FIG. 9
, an external write command signal and an external clock signal transmitted from a tester (not shown) are received in the flip-flop
82
. In the flip-flop
82
, an internal write command signal is set to a high level at a time T
91
in synchronization with a leading edge of a pulse of the external clock signal in a time-period (from a time T
90
to a time T
92
) in which the level of the external write command signal is set to a low level, and the level of the internal write command signal is changed to a low level at a time T
93
in synchronization with a leading edge of a next pulse of the external clock signal in a time-period (after the time T
92
) in which the level of the external write command signal is set to a high level. Because the low level time-period of the external write command signal is equal to the pulse repetition period of the external clock signal, the internal write command signal is set to the high level during a time-period (from the time T
91
to the T
93
) equal to the pulse repetition period of the external clock signal. The internal write command signal is transmitted from the flip-flop
82
to the memory cell array
84
.
Also, the external clock signal and an external pre-charge command signal transmitted from the tester are received in the flip-flop
83
. The external pre-charge command signal is set to a low level during a time-period (from the time T
92
to a time T
95
) which is equal to the pulse repetition period of the external clock signal and is later than the low level time-period of the external write command signal by the pulse repetition period of the external clock signal. In the flip-flop
83
, an internal pre-charge command signal is set to a high level at the time T
93
in synchronization with a leading edge of a pulse of the external clock signal in the time-period (from the time T
92
to a time T
95
) in which the level of the external pre-charge command signal is set to a low level, and the level of the internal pre-charge command signal is changed to a low level at the time T
94
in synchronization with a leading edge of a next pulse of the external clock signal in a time-period (after the time T
95
) in which the level of the external pre-charge command signal is set to a high level. The internal pre-charge command signal is transmitted from the flip-flop
83
to the memory cell-array
84
.
In the memory cell array
84
, an operation test of memory cells is performed in a write recovery time-period (from the time T
91
to the time T
93
) determined by a leading edge of the internal write command signal and a leading edge of the internal pre-charge command signal. Therefore, the write recovery time-period depends on the pulse repetition period of the external clock signal.
However, because the pulse repetition period of the external clock signal is longer than that of a clock signal which is actually used in a normal operation of a semiconductor memory represented by the SDRAM
80
, an operational performance of the semiconductor memory cannot be reliably tested. Therefore the judgment whether or not an operational performance of the semiconductor memory satisfies specifications required of the semiconductor memory cannot be performed in a wafer test. Therefore the judgment is performed in a final test when the semiconductor memory is packaged, and a semiconductor memory not satisfying the specifications required of the semiconductor memory is abandoned. Therefore there is drawbacks that the test performed for the semiconductor memory is troublesome and the semiconductor memory cannot be manufactured at a low cost.
SUMMARY OF THE INVENTION
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional test circuit, a test circuit of a semiconductor memory in which the judgment whether or not an operational performance of the semiconductor memory satisfies specifications required of the semiconductor memory is reliably performed in a wafer test even though an external clock signal having a pulse repetition period longer than that of a clock signal, which is used to operate the semiconductor memory while satisfying the specifications, is used in the wafer test.
The object is achieved by the provision of a test circuit of a semiconductor memory, comprising internal clock enabling signal producing means for producing an internal clock enabling signal set to a first level from a first write recovery test signal set to the first level and an external clock enabling signal, of which a phase is shifted from that of an external clock signal by ½L (L is a positive integer higher than 1) of a pulse repetition period of the external clock signal or which is set to a second level; internal clock signal producing means for producing an internal clock signal, of which a pulse repetition period is, 1/N (N is a positive integer, and N=L for the positive integer higher than 1) of the pulse repetition period of the external clock signal, from the internal clock enabling signal produced by the internal clock enabling signal producing means, the external clock signal, the first write recovery test signal set to the first level and the external clock enabling signal; internal write command signal and internal pre-charge signal producing means for producing an internal write command signal and a first pre-charge signal, of which a leading edge is shifted from that of the internal write command signal by ½N of the pulse repetition period of the external clock signal, from the internal clock signal produced by the internal clock signal producing means, an external write command signal set to the second level, the first write recovery test signal set to the first level and the external clock signal; and a first selector for outputting the first pre-charge signal produc

Affiliated with

Also associated with

Rating

Test circuit of semiconductor memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test circuit of semiconductor memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test circuit of semiconductor memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3152136