Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-07-03
2007-07-03
Ton, David (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S742000
Reexamination Certificate
active
10448331
ABSTRACT:
A test component and method of operation thereof are provided, the test component being arranged in a test environment to issue a test sequence over a bus to a device under test. A configuration file is provided to specify the behaviour of the test component, the configuration file comprising a plurality of regions with each region specifying attributes for use in determining the test sequence. The method of the present invention comprises the steps of: (a) when a test sequence is required to be issued, causing the test component to select, based on predetermined criteria, one of a number of regions provided by the configuration file; and (b) using the constraint attributes for that selected region to generate the test sequence to be issued on to the bus.
REFERENCES:
patent: 5729554 (1998-03-01), Weir et al.
patent: 5862149 (1999-01-01), Carpenter et al.
patent: 6065116 (2000-05-01), Isaacson et al.
patent: 6327687 (2001-12-01), Rajski et al.
patent: 6804803 (2004-10-01), Barnhart et al.
Coley Daniel J
Nightingale Andrew M
Wrigley Christopher E
Arm Limited
Nixon & Vanderhye P.C.
Ton David
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