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Adaptive runtime repairable entry register file

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Adaptive sigma-delta modulation with improved dynamic range

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Adaptive soft demodulation for reception of distorted signals

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Adaptive threshold control circuit and method within high...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
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Adaptive waveform equalization for viterbi-decodable signal...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Adaptor With Clocks For Like Parts of Different Scan Paths

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Add compare select circuit and method implementing a viterbi alg

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Add-compare-select accelerator using pre-compare-select-add...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Add-compare-select arithmetic unit for Viterbi decoder

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Add-compare-select processor in Viterbi decoder

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent

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Address and TMS gating circuitry for TAP control circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Address conversion device for nonvolatile memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Address counter for addressing synchronous high-frequency...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Address counter test mode for memory device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Address decoding system and method for failure toleration in...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Address error detection by merging a polynomial-based CRC...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Address generation apparatus for turbo interleaver and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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Address generation for contention-free memory mappings of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Address generator

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Address generator for block interleaving

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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