Adaptive runtime repairable entry register file

Details Adaptive runtime repairable entry register file Adaptive runtime repairable entry register file

2006-06-20

2006-06-20

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S763000

Reexamination Certificate

active

07065694

ABSTRACT:
Methods and apparatus are disclosed that provide for improved addressing of a register file in a computer system. The register file has one or more redundant words. A logical address in an instruction is mapped, during a predecode operation, to a physical address having a larger address space than the logical address. Addresses of nonfaulty words are mapped to the same word in the larger address space as the logical address. Logical addresses that point to faulty words are mapped to a redundant word that is in the larger address space but not in the address space of the logical address. Because all addresses presented to a register file decoder at access time point to nonfaulty words, no delay penalty associated with address compare during the access time is required.

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