Add compare select circuit and method implementing a viterbi alg

Details Add compare select circuit and method implementing a viterbi alg Add compare select circuit and method implementing a viterbi alg

1998-03-26

2000-11-14

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

375341, 714792, 714797, H03M 1303

Patent

active

061484318

ABSTRACT:
A detector system employing a Viterbi algorithm includes an apparatus and method which constructs a double-state trellis structure for determining a most likely received symbol sequence with respect to an observed sequence of channel output samples. In the double state trellis, pairs of states are identified having equivalent branch metric values which also have a same decision during a path select, thus allowing these pairs of states to share a compare operation of a previous state metric. Consequently, to calculate an updated or current state metric value, an add, compare and select (ACS) circuit may compare only the previous state metric values to determine a minimum value for a transition between two states while combining each previous state metric value with its corresponding branch metric to provide an updated or current state metric value.

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Black, P.J.; Meng, T.H.-Y., "A 140 Mb/s 32-state radix-4 Viterbi decoder", Solid-State Circuits Conferences, 1992. Digest of technical papers. 39th ISSCC, 1992 IEEE International, pp. 70-71, 247.

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