Adaptor With Clocks For Like Parts of Different Scan Paths

Details Adaptor With Clocks For Like Parts of Different Scan Paths Adaptor With Clocks For Like Parts of Different Scan Paths

2011-08-09

2011-08-09

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000

Reexamination Certificate

active

07996740

ABSTRACT:
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

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Girard, P.; Guiller, L.; Landrault, C.; Pravossoudovitch, S.;, “Low power BIST design by hypergraph partitioning: methodology and architectures,” Test Conference, 2000. Proceedings. International, vol., no., pp. 652-661, 2000 doi: 10.1109/TEST.2000.894260.

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