Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-11-28
2006-11-28
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S794000, C375S262000, C375S341000
Reexamination Certificate
active
07143335
ABSTRACT:
An add-compare-select (ACS) arithmetic unit for a Viterbi decoder is provided. The ACS arithmetic unit includes two 2's complement adders for performing an operation on a state metric related to a bit value 0 and a state metric related to a bit value 1, respectively; a 2's complement subtractor for performing a subtraction on the outputs of the two 2's complement adders; a multiplexer for selecting the smaller output between the outputs of the two 2's complement adders; an absolute value calculator for calculating an absolute value of the subtraction result of the 2's complement subtractor; a look-up table for calculating a log value corresponding to the absolute value generated from the absolute value calculator; and a subtractor for subtracting the log value, which is provided from the look-up table, from the output of the multiplexer to output a state metric Since the ACS arithmetic unit does not need a comparator, a MUX, and a subtractor, which are necessary for normalization, it can use a high system clock signal Consequently, entire throughput can be increased, and latency can be decreased.
REFERENCES:
patent: 5075879 (1991-12-01), Anderson
patent: 5546335 (1996-08-01), Lee
patent: 5905662 (1999-05-01), Shiraishi
patent: 6370097 (2002-04-01), Hayashi et al.
patent: 6813744 (2004-11-01), Traeber
patent: 6865710 (2005-03-01), Bickerstaff et al.
patent: 2000-0075096 (2000-12-01), None
C. Bernard Shung, et al., “VLSI Architectures for Metric Normalization in the Viterbi Algorithm”, Proceeding of IEEE International Conference on Communications, No. 16-19, pp. 1723-1728, Apr. 1990.
Abraham Esaw T.
De'cady Albert
Sughrue & Mion, PLLC
LandOfFree
Add-compare-select arithmetic unit for Viterbi decoder does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Add-compare-select arithmetic unit for Viterbi decoder, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Add-compare-select arithmetic unit for Viterbi decoder will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3686632