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Array-built-in-self-test (ABIST) for efficient, fast,...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate

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ASIC BIST employing stored indications of completion

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Asic control and data retrieval method and apparatus having an i

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent

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ASIC logic BIST employing registers seeded with differing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Assembly and method for testing integrated circuit devices

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Assembly for LSI test and method for the test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Assisted memory device for reading and writing single and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Assisted memory system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Assuring sequence number availability in an adaptive...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Asymmetric error correction apparatus and method, and clock...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error detection for synchronization control
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Asynchronous bist for embedded multiport memories

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Asynchronous communication apparatus using JTAG test data...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Asynchronous control of memory self test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Asynchronous debug interface

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Asynchronous integrated circuit tester

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Asynchronous set-reset circuit device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Asynchronous testing of reset operation in an integrated...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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At speed testing asynchronous signals

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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At-speed ATPG testing and apparatus for SoC designs having...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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At-speed scan testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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