Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1997-02-27
1999-08-17
Nguyen, Hoa T.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
714727, 714733, 714734, 714724, G01R 3128, G11C 2900
Patent
active
059387793
ABSTRACT:
ASIC (Application-Specific Integrated Circuit) testability, troubleshooting access and visibility of internal circuitry are the primary targets of test engineering analysis. The widely applied boundary-scan technique is a useful interface but does not solve all problems connected with the PBA (Printed Board Assembly) manufacturing process. The invention provides an extension of the boundary-scan technique currently implemented to provide improved ASIC testability. The Collateral ASIC Test (method and logic) implemented in a boundary-scan device according to the invention makes possible a test process standardization to ASIC design and testing.
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Alcatel Alsthom Compagnie Generale d'Electricite
Nguyen Hoa T.
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