Asynchronous control of memory self test

Details Asynchronous control of memory self test Asynchronous control of memory self test

2007-04-10

2007-04-10

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S733000, C714S031000

Reexamination Certificate

active

10861247

ABSTRACT:
A memory logic built-in self-test (“BIST”) includes slow speed controller-to-collar signals, while allowing collars to test memories at full speed. A controller is configured to include control features and address, data, read/write, output evaluation, and redundancy calculation values are configured within the collars. The controller is further configured to handle scheduling of the collars and diagnostics interfacing. In addition, the collars are configured to allow BIST testing to be run serially, in parallel, or in groups. Collars are also configured to send diagnostic results back to the controller based on the initialization of the respective collars, thus providing a central interface for the diagnostics results.

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