Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2011-03-08
2011-03-08
Ton, David (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S718000
Reexamination Certificate
active
07904786
ABSTRACT:
A memory system comprises a plurality of memory storage elements, an address sparing module coupled to the plurality of memory storage elements and operable to map first addresses of first predetermined memory locations to second addresses of second predetermined memory locations, and an ECC (error correcting cod) combinatorial logic circuit coupled to the plurality of memory storage elements and operable to detect and correct errors in data read from the plurality of memory storage elements in less than three clock cycles.
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Eldredge Kenneth J.
Hilton Richard L.
Hewlett--Packard Development Company, L.P.
Ton David
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