Architecture and control of reed-solomon error-correction...

Architecture and control of reed-solomon list decoding

Architecture and method for testing of an integrated circuit...

Architecture for a message bus

Architecture for an iterative decoder

Architecture for built-in self-test of parallel optical...

Architecture for soft decision decoding of linear block...

Architecture of an efficient at-speed programmable memory...

Architecture, circuitry and method for testing one or more...

Area efficient BIST system for memories

Area efficient memory architecture with decoder self test...

Area efficient parallel turbo decoding

Area optimized edge-triggered flip-flop for high-speed...

Area-efficient convolutional decoder

Area-efficient surviving paths unit for Viterbi decoders

Arithmetic built-in self-test of multiple scan-based...

Arithmetic circuit

Arithmetic operation method for cyclic redundancy check and...

Arithmetic unit performing cyclic redundancy check at high...

ARQ combining holdoff system and method