Architecture for an iterative decoder

Details Architecture for an iterative decoder Architecture for an iterative decoder

2007-09-25

2007-09-25

Lamarre, Guy (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S795000, C714S793000

Reexamination Certificate

active

10926063

ABSTRACT:
Iterative decoder comprising a plurality of servers which perform the iterative decoding of a data block each, an input buffer memory and a control unit which performs a statistical multiplexing of the data at input, which are firstly stored in the input buffer memory and successively processed by one of the servers. The input buffer memory comprises N+L memory locations, where N is the number of servers and L is the number of so-called additional locations. Each block to be decoded which is received while all the servers are busy is stored in one of the L additional locations possibly available, or it is lost if the input buffer memory is entirely filled. The number L of additional locations and the number N of servers are such that the probability PBof a block being lost, calculated on the basis of a queuing model of D/G/N/N+L type, satisfies the condition PB≦α·FER*, where FER* is the error rate in the blocks allowed and α<1; typically α is of the order of 0.01. Process for manufacturing such an iterative decoder comprising a step of design and a step of hardware embodiment.

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