Arithmetic circuit

Details Arithmetic circuit Arithmetic circuit

2011-03-22

2011-03-22

Lamarre, Guy J (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S795000, C375S262000, C375S341000

Reexamination Certificate

active

07913153

ABSTRACT:
An arithmetic circuit includes a NOR circuit for outputting 1-bit inverted logical OR sf from all of a first bit group x(6) to x(10) containing0or more high-order bit of a path metric value composed of a plurality of bits, an inverter for inverting each bit of a second bit group x(2) to x(5) and outputting a third bit group rs(0) to rs(3), an AND circuit for outputting a fourth bit group ns(0) to ns(3) that contain results of calculating a logical AND of sf and rs(0) to rs(3), and a CF output section for outputting a correction factor CF based on ns(0) to ns(3).

REFERENCES:
patent: 7162675 (2007-01-01), Das et al.
patent: 2007/0011601 (2007-01-01), Griseta et al.
patent: 1 162 750 (2001-12-01), None
patent: 1 507 332 (2005-02-01), None
patent: 2002-100995 (2002-05-01), None
patent: 2002-344330 (2002-11-01), None
patent: 2004-80508 (2004-03-01), None
patent: 2004-194326 (2004-07-01), None
A. Taffin, “Generalized stopping criterion for iterative decoders”, IEEE Electronics Letters, vol. 39, No. 13, Jun. 26, 2003.
United Kingdom Search Report dated Jun. 30, 2008.
United Kingdom combined Search Report and Office Action dated Aug. 28, 2007.

Affiliated with

Also associated with

Rating

Arithmetic circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Arithmetic circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Arithmetic circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2726130