Circuit for verifying the write speed of SRAM cells
Circuit structure and method for stress testing of bit lines
Circuit which provides power on reset disable during a test mode
Circuitry and methodology to test single bit failures of integra
Circuitry for a programmable element
Circuitry, apparatus and method for embedding quantifiable...
Circuits and methods for burn-in of integrated circuits using po
Circuits and methods for generating high frequency extended...
Circuits and methods for testing memory cells along a...
Circuits and systems for realigning data output by...
Circuits for testing memory devices having direct access test mo
Circuits, systems and methods for testing integrated circuit dev
CMOS cell and circuit design for improved IDDQ testing
CMOS memory margining control circuit for a nonvolatile memory
CMOS static RAM testability
Column redundancy circuit for a semiconductor memory device
Compressed input/output test mode
Computer memory with status cell
Configurable self-test for embedded RAMs
Configure registers and loads to tailor a multi-level cell...