Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-01-31
2002-10-01
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S185200, C365S189070
Reexamination Certificate
active
06459634
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to circuitry and methods for testing a memory device More particularly, the present invention provides circuitry and methods for testing memory cells of an edge of an array of memory cells.
Referring to
FIG. 1
, a known exemplary memory cell
102
comprises capacitor
104
and a transistor
108
coupled in series therewith as a switch for selectively accessing the capacitor. One plate, or electrode
101
, of the capacitor is coupled to a common node. The other electrode
103
of the capacitor serves as a storage electrode for the memory cell. The transistor
108
typically comprises a MOSFET transistor and has its gateable channel electrically coupled between the storage electrode
103
of the capacitor and a bitline
106
.
For a semiconductor memory device, e.g., a Dynamic Random Access Memory (DRAM), referencing
FIGS. 2A
,
2
B, a plurality of memory cells
102
are arranged in rows and columns, e.g., as an x-y grid, to provide an array
200
of memory cells. Conductive bitlines
105
,
106
extend a length of the array and connect bitline contacts
122
of respective columns. Wordlines
110
extend widths of the array and connect control terminals of the access transistors of their respective rows. Known address decode circuitry
109
,
107
determines, in accordance with supplied address data, select bitlines and wordlines upon which to propagate data and enable signals respectively.
Further referencing
FIGS. 2A
,
2
B, known decode circuitry
109
drives wordlines
110
in accordance with received address data. When activated by the decode circuitry, a wordline propagates an enable signal for enabling access transistors of its row of memory cells. Once the access transistors are enabled, data of the true or complementary bitlines
105
,
106
respectively, is transferred provide data for transfer into capacitors of the memory cells of the selected row. Alternatively, during a read operation, data is transferred from the capacitors to the bitlines.
Within the present disclosure, the terms “one” and “zero” will refer to high and low data or logic levels respectively. Additionally, an enable signal may be thought of as enabling when active high. Notwithstanding the above, the present disclosure is deemed to encompass reverse or complementary perspectives thereof.
Further referencing
FIGS. 2A
,
2
B, known sense amplifiers
114
sense and differentially amplify voltage levels of the true and complementary bitlines
105
,
106
in accordance with data provided thereto. Know input/output buffers and column decoders
107
decode address data and propagate data upon select bitlines as determined by the address data. Known equilibration circuits
115
equilibrate the true and complementary bitlines
105
,
106
to an equilibration bias level, i.e., of equilibration node
117
, before the sense amplifiers are enabled. Equilibration node
117
is typically biased with the intermediate voltage level (e.g., DVC
2
). Known bus or supply circuitry distribute an upper voltage, e.g., V
CC
, lower voltage, e.g., Ground, and the intermediate voltage, e.g., V
cc
/2, about the memory device.
In normal operation, a high data level is stored within a memory cell by biasing a bitline with an upper logic level, e.g., V
cc
, and activating a wordline
110
with an enable signal for enabling the memory cell's access transistor and transferring the upper voltage level (V
cc
) of the bitline into the memory cell's storage electrode. Assuming an intermediate voltage bias at the common electrode
101
of, e.g., V
cc
2, a positive voltage difference, e.g.,+V
cc
/2, is provided for storage between the storage and common electrodes of the memory cell's capacitor
104
. Thereafter, the wordline is deactivated for disabling the access transistor and isolating the storage electrode from the bitline. Likewise, a low data level may be stored within the memory cell using a similar procedure but with the bitline biased at the lower logic level, e.g., ground, during the write cycle, thereby providing a negative voltage difference, e.g.,−V
cc
/2, between the storage and common electrodes of the capacitor.
It will be understood that the present description of a known exemplary dynamic random access memory (DRAM) and its operation is meant to provide a general understanding of a DRAM and is not meant to provide a complete description thereof.
Further referencing
FIG. 2B
, two separate storage node contacts at distal ends of active regions
120
are electrically coupled to the storage electrodes of respective memory cell capacitors. Accordingly, one of the cells employs one-half of active region
120
while the other, adjacent cell employs the other half of the active region. Two different row wordlines
110
overlap respective portions of active region
120
and form transistor gates thereover for controlling channels of their respective access transistors, which in turn enable selective coupling of the memory cell capacitors to a shared column bitline
105
(
106
) by way of a bitline contact
122
between the two wordlines.
FIG. 3
portrays, in simplified view, exemplary storage node electrodes of memory cell capacitors of a memory array. Wordlines
110
are schematically illustrated in order to facilitate an understanding of placements of the storage electrodes. During fabrication of the memory array, a defect
130
may result between adjacent capacitors, for example, between storage electrodes
132
and
134
. It is theorized that such defect
130
could be caused, for example, by residual polysilicon particles settling between the electrodes during fabrication of the array. In schematic representation, referencing
FIG. 4
, defect
130
provides a resistive path between the storage electrodes
132
,
134
of neighboring capacitors
104
A
and
104
B
. Accordingly, data of a “one” level stored at capacitor
104
A
might bleed-off and into a neighboring capacitor
104
B
so as to potentially corrupt their data contents, assuming capacitor
104
B
stores a “zero” level.
During the manufacture of semiconductor memory, known tests screen the memory for defects and assure quality of shipped product. For a memory device comprising, for example, a dynamic random access memory (DRAM), one known test comprises writing a checker-board pattern of data—e.g., alternating 1's and 0's—into memory cells of the array in order to check the cell-to-cell isolation between neighboring memory cells. U.S. Pat. No. 5,657,284, entitled “Apparatus and Method for Testing Defects Between Memory Cells In Packaged Semiconductor Memory Devices,” discloses one such exemplary test method that writes alternating “one” and “zero” data levels of the checkerboard test pattern into an array of memory cells. When writing, for example, a designated “one” cell, a high data level is applied to the storage electrode of the designated “one” cell for a duration sufficient to bring-out (or effect a current flow through) a potential short-circuit defect to an adjacent “zero” cell, i.e., of a zero data level. Checking the values of the adjacent “zero” cells after writing the designated “one” cell enables determination of potential cell-to-cell defects. U.S. Pat. No. 5,657,284 is assigned to the assignee of the present application and is incorporated herein by reference.
It is known to provide dummy cells around the periphery of a memory array in order to assist process uniformity during fabrication of the array of memory cells. Referencing
FIG. 5
, the known checkerboard pattern of test data within the array of memory cells stresses and tests the cell-to-cell isolation between inner cells of the array. However, memory cells at the periphery of the memory array receive stressing and testing relative to the inner cells of the array without significant testing external thereto. The known dummy cells of the exemplary prior art which neighbor a peripheral row of the array, have their wordline grounded (See
FIG. 2B
) to disable their associated access transistors (
Elms Richard
Howrey Simon Arnold & White , LLP
Micro)n Technology, Inc.
Nguyen Tuan T.
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