Circuits for testing memory devices having direct access test mo

Details Circuits for testing memory devices having direct access test mo Circuits for testing memory devices having direct access test mo

1998-11-24

2000-10-31

Elms, Richard

Static information storage and retrieval

Read/write circuit

Testing

365193, G11C 700

Patent

active

061412716

ABSTRACT:
An integrated circuit memory device includes a test mode. Data is written to and read from the integrated circuit memory device in the test mode. The integrated circuit memory device includes a memory array that includes memory cells that store data. A test control circuit generates control signals that control the data read from the memory cells. A data output circuit outputs data read from the memory cells from the integrated circuit memory device in response to the test column address strobe signal. In particular, the test column address strobe signal includes a series of high to low and low to high transitions, wherein the data output circuit outputs data read from the memory cells in response to the series of high to low and low to high transitions. The high to low and low to high transitions of the test column address strobe signal may be used to output the data read from the memory cells, thereby reducing the need for an external test clock signal to be supplied to the integrated circuit memory device during testing.

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European Search Report, EP 98 30 3712, Sep. 28, 1998.

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