CMOS memory margining control circuit for a nonvolatile memory

Details CMOS memory margining control circuit for a nonvolatile memory CMOS memory margining control circuit for a nonvolatile memory

1986-02-28

1987-04-14

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Testing

G11C 2900, G11C 1140

Patent

active

046583807

ABSTRACT:
A circuit for enabling off-chip measurement of an on-chip generated reference voltage and for effectuating the memory margin testing of nonvolatile memory cells in wells of a CMOS integrated circuit chip. The circuit is configured to selectively couple off-chip voltages of positive and negative potential to nodes on the chip while avoiding undesired forward biasing of p-n junctions. Control is initiated by varying the functions the input pads perform.

REFERENCES:
patent: 4223394 (1980-09-01), Pathak et al.
patent: 4418403 (1983-11-01), O'Toole et al.
patent: 4459686 (1984-07-01), Toyoda
patent: 4502140 (1985-02-01), Proebsting

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