Circuitry and methodology to test single bit failures of integra

Details Circuitry and methodology to test single bit failures of integra Circuitry and methodology to test single bit failures of integra

1995-08-24

1997-05-27

Zarabian, Amir

Static information storage and retrieval

Read/write circuit

Testing

365190, G11C 700

Patent

active

056338287

ABSTRACT:
According to the present invention, a structure and method provides for single bit failures of an integrated circuit memory device to be analyzed. According to the method for analyzing a single bit failure of an integrated circuit memory device, a test mode is entered, bitline load devices of the integrated circuit memory device are turned off, a single bit of the integrated circuit memory device is selected, the device is placed into a write mode, a plurality of bitlines true and a plurality of bitlines complement of the integrated circuit memory device not associated with the single bit are then set to a low logic level, the bitline true and the bitline complement associated with the single bit is connected to a supply bus and a supply complement bus which is connected to test pads. Finally, the electrical characteristics of the single bit can be monitored on the test pads. According to the structure of the present invention, bitline load devices of the integrated circuit memory device are controlled by a test mode signal, the state of which determines when the test mode will be entered. These bitline load devices are connected to the bitlines true and complement which in turn are connected to the memory cell. Select devices, such as column select transistors, are connected to the bitline true and bitline complement; they are also connected to driver circuitry by a bus, such as a write bus, a read bus or a write/read bus. The driver circuitry is supplied with supply voltages as well as data signals. Further, a buffer circuit allows bitlines true and bitlines complement not associated with the single bit being tested to be pulled to a logic low level. A dummy structure also provides the opportunity to directly monitor the bitlines of the integrated circuit memory device without the need for microprobing.

REFERENCES:
patent: 4962487 (1990-10-01), Suzuki
patent: 5453954 (1995-09-01), Nakamura
patent: 5463585 (1995-10-01), Sanada

Affiliated with

Also associated with

Rating

Circuitry and methodology to test single bit failures of integra does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuitry and methodology to test single bit failures of integra, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuitry and methodology to test single bit failures of integra will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2333876