CMOS static RAM testability

Details CMOS static RAM testability CMOS static RAM testability

1992-11-18

1994-11-01

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

371 211, 365203, G01R 3128

Patent

active

053612329

ABSTRACT:
An apparatus and method for improving the testability of six cell CMOS SRAM circuits. The technique involves adding transistors and the ability to effectively disable the precharge circuitry during the test mode. This makes the pull up transistors the only current source for switching the memory cell. An open or weak pull up transistor, which would appear as an intermittent soft failure under operational conditions because of the current sourcing of the precharge circuitry, becomes a hard stuck-at failure under the test conditions. Because the precharge circuitry is disabled for all memory cells, a slower memory clock speed is used for memory cycling during the test mode.

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patent: 5034923 (1991-07-01), Kuo et al.
patent: 5136545 (1992-08-01), Takayanagi
patent: 5166608 (1992-11-01), Bowles
patent: 5255230 (1994-10-01), Chan et al.

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