Compressed input/output test mode

Details Compressed input/output test mode Compressed input/output test mode

1997-07-28

1999-12-28

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

36523005, 36518907, 371 211, 371 2231, G11C 700

Patent

active

06009026&

ABSTRACT:
The present invention discloses a system and method of testing semiconductor memory devices formed as integrated circuits on semiconductor substrates. The present invention allows parallel testing of arrays using only one input/output (I/O or DQ) to write to the arrays and only two DQs to read from the arrays. The broad search should be directed to methods of compressing the time and number of I/O's required for testing wide, high pin count, or highly partitioned memory arrays. The specific method of this invention comprises simultaneously writing the same test bit to each array, simultaneously reading a common address from each array and comparing the output of each array to report a fail if all outputs are not the same.

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