Static information storage and retrieval – Read/write circuit – Testing
Patent
1994-06-29
1995-10-03
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Testing
365226, G11C 700
Patent
active
054557992
ABSTRACT:
According to the present invention, a special operating mode of an integrated circuit device, such as a stress test mode, is entered while the integrated circuit device is powered up in order to avoid the large switching transients from multiple rows and columns being enabled simultaneously which would result if the stress test mode was entered after the integrated circuit device is powered up. Hence, power on reset can not be avoided by waiting until the power-on reset pulse is generated. The power on reset pulse of the integrated circuit device may be overridden or effectively disabled during a stress test mode, such that potential contention between the power-on reset pulse and the test mode signal of the integrated circuit device is eliminated. As a result, crowbar current is accordingly eliminated so that proper state initialization during a stress test mode may be accomplished.
REFERENCES:
patent: 5345424 (1994-09-01), Landgraf
patent: 5349586 (1994-09-01), Katsuta
McClure David C.
Teel Thomas A.
Jorgenson Lisa K.
Larson Renee M.
Nelms David C.
Robinson Richard K.
SGS-Thomson Microelectronics Inc.
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